參數(shù)資料
型號(hào): SLE 24C02
廠商: SIEMENS AG
元件分類: DRAM
英文描述: 2Kbit (256 ×8 bit) Serial CMOS-EEPROM with IIC Synchronous 2-Wire Bus(2K位(256 ×8 位)串行CMOS-EEPROM)
中文描述: 2Kbit(256 × 8位)串行的CMOS EEPROM,帶有國(guó)際進(jìn)口同步2線巴士(2K位(256 × 8位)串行的CMOS EEPROM的)
文件頁(yè)數(shù): 10/28頁(yè)
文件大?。?/td> 356K
代理商: SLE 24C02
SLx 24C01/02/P
Semiconductor Group
10
1999-02-02
5
After a START condition, the master always transmits a Command Byte CSW or CSR.
After the acknowledge of the EEPROM a Control Byte follows, its content and the
transmitter depend on the previous Command Byte. The description of the Command
and Control Bytes is shown in
table 2
.
Device Addressing and EEPROM Addressing
The device has an internal address counter which points to the current EEPROM
address.
The address counter is incremented
– after a data byte to be written has been acknowledged, during entry of further data
byte
– during a byte read, thus the address counter points to the following address after
reading a data byte.
Command Byte
Selects operation:
the least significant bit b0 is low for a write
operation (Chip Select Write Command Byte CSW) or set high for a
read operation (Chip Select Read Command Byte CSR). In both
Command Bytes, the bit positions b3 to b1 are left undefined.
Following CSW (b0 = 0):
contains the seven or eight lower bits of
the EEPROM address (EEA) bit A6 or A7 to A0, or an additional
command byte for the handling of the protection bit.
Following CSR (b0 = 1):
contains the data read out, transmitted by
the EEPROM. The EEPROM data are read as long as the master
pulls down SDA after each byte in order to acknowledge the transfer.
The read operation is stopped by the master by releasing SDA (no
acknowledge is applied) followed by a STOP condition.
Control Byte
Table 2
Command and Control Byte for
I
2
C-Bus Addressing of Chip and EEPROM
Definition
b7
b6
b5
b4
b3
b2
CSW
1
0
1
0
x
x
CSR
1
0
1
0
x
x
EEA
A7
A6
A5
A4
A3
A2
Function
b1
x
x
A1
b0
0
1
A0
Chip Select for Write
Chip Select for Read
EEPROM address
相關(guān)PDF資料
PDF描述
SLA 24C04 4 Kbit (512 ×8 bit) Serial CMOS-EEPROM with IIC Synchronous 2-Wire Bus(4K位 (512 ×8 位)CMOS串行EEPROM(帶IIC控制))
SLE 24C04 4 Kbit (512 ×8 bit) Serial CMOS-EEPROM with IIC Synchronous 2-Wire Bus(4K位 (512 ×8 位)CMOS串行EEPROM(帶IIC控制))
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