- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98082 > SLC88B17QFP (STANDARD MICROSYSTEMS CORP) ISA BUS CONTROLLER, PQFP160 PDF資料下載
參數(shù)資料
| 型號： | SLC88B17QFP |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | ISA BUS CONTROLLER, PQFP160 |
| 封裝： | QFP-160 |
| 文件頁數(shù)： | 4/54頁 |
| 文件大?。?/td> | 333K |
| 代理商： | SLC88B17QFP |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
SMSC DS – SLC88B17
Page 12
Rev. 09/28/99
nDACK[0]
I/O
DMA Acknowledge. This pin is normally used to return DMA acknowledge signal
for DMA channel 0 in response to its data transfer request.
During reset, the SLC88B17 also senses the voltage level of the nDACK0 pin. If it is
pulled down to VSS externally, the SLC88B17 will claim (i.e. positively decode) all
PCI memory cycles whose address falls in the range of 0FFF0000h to 0FFFFFFFh,
and forward them to the ISA bus.
nDACK[1-3]
nDACK[5-7]
O
DMA Acknowledge. DMA acknowledge signals for the corresponding requests. If
the DREQ goes inactive before nDACK being asserted, the nDACK signal will not
be asserted.
During Reset: High
After Reset: High
nISAREQ
O
ISA DMA Request. This is DMA requests for PC/PCI protocol.
nISAGNT
I
ISA DMA Grant. This is DMA grant for PC/PCI protocol.
During Reset: High
After Reset: High
TC
O
Terminal Count. Terminal count indicator. The SLC88B17 asserts TC after a new
address has been output and the byte count expires with that transfer. TC remains
asserted until AEN is negated, unless AEN is negated during an auto initialization.
TC is negated before AEN is negated during an auto initialization.
nREFRESH
I/O
Refresh Request. As an output, nREFRESH is used to indicate when a refresh is in
progress. The SA[7-0] should be applied to all banks of DRAM on the ISA bus so
that when nMEMR is asserted, the entire expansion bus DRAM is refreshed. This
signal is an output only when the SLC88B17 DMA controller is a master on the bus
responding to the internally generated request for refresh. It is an input signal during
ISA master cycles.
During Reset: High-Z
After Reset: High
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SLF4000L7 | 2-INPUT NAND GATE, BCC7 |
| SLHNNGAL32ANT | SINGLE COLOR LED, GREEN, 5.2 mm |
| SLHNNWH511T0S0QRC3 | SINGLE COLOR LED, WHITE, 5.6 mm |
| SLHNNWH531T0S0QRC5 | SINGLE COLOR LED, COOL WHITE, 5.6 mm |
| SLHNNWH531T0S0QRC5 | T-3 SINGLE COLOR LED, COOL WHITE, 8 mm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SLC8B1300 | 制造商:ITT 制造商全稱:ITT Industries 功能描述:Snap/Clip-Lock Environmentally Sealed - Circular |
| SLC8B1310 | 制造商:ITT 制造商全稱:ITT Industries 功能描述:Snap/Clip-Lock Environmentally Sealed - Circular |
| SLC8B500 | 制造商:ITT 制造商全稱:ITT Industries 功能描述:Snap/Clip-Lock Environmentally Sealed - Circular |
| SLC8B510 | 制造商:ITT 制造商全稱:ITT Industries 功能描述:Snap/Clip-Lock Environmentally Sealed - Circular |
| SLC8P1300 | 制造商:ITT 制造商全稱:ITT Industries 功能描述:Snap/Clip-Lock Environmentally Sealed - Circular |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。