參數(shù)資料
型號: SLA24C32-D
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 32 Kbit 4096 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus
中文描述: 4K X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8
封裝: PLASTIC, DIP-8
文件頁數(shù): 24/26頁
文件大小: 357K
代理商: SLA24C32-D
SLx 24C32
Semiconductor Group
24
Preliminary 1998-07-27
1)
The minimum rise and fall times can be calculated as follows: (20 + (0.1/pF)
×
C
b
) ns
Example:
C
b
= 100 pF
t
R
= (20 + 0.1
×
100) ns = 30 ns
8.3
Parameter
AC Characteristics
Symbol
Limit Values
V
CC
= 2.7-5.5 V
min.
Limit Values
V
CC
= 4.5-5.5 V
min.
Units
max.
100
max.
400
SCL clock frequency
Clock pulse width low
Clock pulse width high
SDA and SCL rise time
SDA and SCL fall time
Start set-up time
Start hold time
Data in set-up time
Data in hold time
SCL low to SDA data out valid
Data out hold time
Stop set-up time
Time the bus must be free before
a new transmission can start
SDA and SCL spike suppression
time at constant inputs
f
SCL
t
low
t
high
t
R
t
F
t
SU.STA
t
HD.STA
t
SU.DAT
t
HD.DAT
t
AA
t
DH
t
SU.STO
t
BUF
kHz
μ
s
μ
s
ns
ns
μ
s
μ
s
ns
μ
s
μ
s
ns
μ
s
μ
s
4.7
4.0
1.2
0.6
1000
300
1)
300
300
1)
4.7
4.0
200
0
0.1
100
4.0
4.7
0.6
0.6
100
0
0.1
50
0.6
1.2
4.5
0.9
t
l
50
100
50
100
ns
8.4
Parameter
Erase and Write Characteristics
Symbol
Limit Values
V
CC
= 2.7-5.5 V
typ.
5
2.5
2.5
Limit Values
V
CC
= 4.5-5.5 V
typ.
5
2.5
2.5
Units
max.
8
4
4
max.
8
4
4
Erase + write cycle (per page)
Erase page protection bit
Write page protection bit
t
WR
ms
ms
ms
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參數(shù)描述
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