參數(shù)資料
型號(hào)： SLA24C32-D-3
廠商： SIEMENS A G
元件分類(lèi)： DRAM
英文描述： 32 Kbit 4096 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus
中文描述： 4K X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8
封裝： PLASTIC, DIP-8
文件頁(yè)數(shù)： 21/26頁(yè)
文件大?。?/td> 357K
代理商： SLA24C32-D-3
SLx 24C32
Semiconductor Group
Preliminary 1998-07-27
31 bytes have to be identical to the bytes stored in ascending address order within the
same page.
A successful verification of each byte is indicated by the EEPROM by pulling the SDA
line to low (acknowledge ACK).
The bit programming procedure is initiated by the STOP condition after verification of the
last byte. Programming is started only if all 256 bits of a page have been verified
successfully. If bit programming has taken place, the address counter points to the
uppermost address of the respective page. The write or erase cycle is finished latest
after 4 ms. Acknowledge polling can be used for speed enhancement in order to detect
the end of the write or erase cycle (refer to
chapter 5.3,
Acknowledge Polling).
7.3
The byte sequence for random bit read is shown in
figure 17
.
Protection Bit Read
Figure 17
Byte Sequence for Protection Bit Read
The first command byte CSW followed by the address bytes AHI/ALO determine the
protection bit to be read. The second command byte CSW is followed by the control byte
00
H
for protection bit read. The first bit (MSB) of the transferred byte is the protection bit
of the addressed page. The other 7 bits are not valid. The page protection status is
indicated as follows:
Protection Bit = 1: A normal write operation changes the data in the associated page
Protection Bit = 0: The data in the associated page are protected against changes.
If the master acknowledges a byte with a low state of the SDA line, the protection bit of
the next page can be read as the first bit of the following byte. If the master releases the
SDA line, a STOP condition has to complete the read procedure. Any number of bytes
with a page protection status at the first bit position can be requested by the master. After
the bit of the uppermost page has been addressed an overflow of the address counter
occurs and the protection bit of the first page will be read next.
0
0
0
0 0 0
0 0
C
K
A
C
K
A
...
IED02524
C
K
A
b
b
b
S
S
P
O
P
S
T
S
T
R
T
A
S
T
R
T
A
b = Protection Bit
Bus Activity
EEPROM
SDA Line
Activity
Master
Bus
Byte n
Byte n+1
Command
Byte
CSW
Data
Control
Byte
CTR
Data
Address
AHI
EEPROM
Command
Byte
CSW
Address
ALO
EEPROM
C
K
A
C
K
A
C
K
A
A
C
K
A
C
K
0
相關(guān)PDF資料
PDF描述
SLA24C32-S-3 32 Kbit 4096 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus
SLA24C64-D 64 Kbit 8192 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus
SLE24C64-D 16MM ILLUM 65168-013
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SLA24C32-D-3/P 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:32 Kbit 4096 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus
SLA24C32-S 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:32 Kbit 4096 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus
SLA24C32-S/P 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:32 Kbit 4096 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus
SLA24C32-S-3 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:32 Kbit 4096 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus
SLA24C32-S-3/P 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:32 Kbit 4096 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus
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