參數(shù)資料
型號(hào)： SL74HC595N
廠商： System Logic Semiconductor Co., Ltd.
英文描述： 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs
中文描述： 8位Serial-Input/Serial或并行輸出移位與鎖存3注冊(cè)態(tài)輸出
文件頁(yè)數(shù)： 4/5頁(yè)
文件大?。?/td> 47K
代理商： SL74HC595N
IN74HC244
S ystem Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
°
C to
-55
°
C
≤
85
°
C
≤
125
°
C
Unit
t
PLH
, t
PHL
Maximum Propagation Delay, A to YA or B to YB
(Figures 1 and 3)
2.0
4.5
6.0
96
18
15
115
23
20
135
27
23
ns
t
PLZ
, t
PHZ
Maximum Propagation Delay , Output Enable to
YA or YB (Figures 2 and 4)
2.0
4.5
6.0
110
22
19
140
28
24
165
33
28
ns
t
PZL
, t
PZH
Maximum Propagation Delay , Output Enable to
YA or YB (Figures 2 and 4)
2.0
4.5
6.0
110
22
19
140
28
24
165
33
28
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
C
IN
Maximum Input Capacitance
-
10
10
10
pF
C
OUT
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
-
15
15
15
pF
Power Dissipation Capacitance (Per Buffer)
Typical @25
°
C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC
2
f+I
CC
V
CC
34
pF
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Test Circuit
Figure 4. Test Circuit
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