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參數(shù)資料
| 型號(hào)： | SL70D0948 |
| 廠商： | System Logic Semiconductor Co., Ltd. |
| 元件分類： | LED驅(qū)動(dòng)器 |
| 英文描述： | 48 OUTPUT LED DRIVER / 9 BIT PWM CONTROLLER |
| 中文描述： | 48輸出LED驅(qū)動(dòng)器/ 9位PWM控制器 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 149K |
| 代理商： | SL70D0948 |
SLS System Logic Semiconductor
SL70D0948
PIN DESCRIPTION
PIN NAME
FUNCTION
V D D
5 V Power supply terminal.
G N D
GND terminals for LED Drivers and control logic.
All GND terminals must be connected to GND level.
Do not left any GND terminal to NC.
D I N 8 ~ D I N 0
Data input terminals for 9bit R, G, B data.
Shift register accepts R, G, B data from these terminals.
(at rising edge of SHCLK)
D O U T 8 ~ D O U T 0
Output terminals of shift register output data for next
DIN8 ~ DIN0 terminals.
/R E S E T
Reset input terminal (Low active).
S H C L K
Shift register clock input terminal.
S T R O B E
Strobe signal input terminal. At rising edge of strobe signal,
48 channels of 9 bit data registers copy R, G, B data from
shift register.
/C E 1
Chip enable signal input terminal (Low active).
C E 2
Chip enable signal input terminal (High active).
The device accepts SHCLK and STROBE when /CE1 = “L ”
a n d C E 2 = “H ”.
O E B
Output enable signal input terminal.
The device outputs data when OEB = “L ”. W h e n O E B = “H ”
all R, G, B output terminals hold high-impedance state.
P W C L K
PWM generator reference clock input terminal.
B R M O D E
Brightness control mode input terminal.
B R D 2 ~ B R D 0
Brightness control data input terminal.
PIN No.
(MQFP)
49,52,53,54,78,99
9, 16, 23, 33,
34, 41, 48,
59, 65, 72,74
84, 91, 98
100, 1, 2,
3, 4, 5,
6, 7, 8
32, 31, 30,
29, 28, 27,
26, 25, 24
8 3
8 2
8 1
8 0
7 9
7 6
7 7
7 5
56, 57, 58
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