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參數(shù)資料
| 型號： | SL28SRC04BZI |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK 4PCIE GEN3 20TSSOP |
| 標準包裝： | 62 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 時鐘，晶體 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 100MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應商設備封裝： | * |
| 包裝： | * |
SL28SRC04
............... Document #: SP-AP-0757 (Rev. 0.2) Page 2 of 13
Pin Definitions
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
Pin No.
Name
Type
Description
1
VDD
PWR 3.3V Power supply
2
SDATA
I/O
SMBus compatible SDATA.
3
SCLK
I
SMBus compatible SCLOCK.
4
VDD
PWR 3.3V power supply
5
VSS
GND
Ground
6
VDD
PWR 3.3V power supply
7
VSS
GND
Ground
8
SRC1
O, DIF 100 MHz Differential serial reference clocks.
9
SRC1#
O, DIF 100 MHz Differential serial reference clocks.
10
VSS
GND
Ground
11
SRC2
O, DIF 100 MHz Differential serial reference clocks.
12
SRC2#
O, DIF 100 MHz Differential serial reference clocks.
13
VDD
PWR 3.3V power supply
14
VDD
PWR 3.3V power supply
15
SRC3#
O, DIF 100 MHz Differential serial reference clocks.
16
SRC3
O, DIF 100 MHz Differential serial reference clocks.
17
VSS
GND
Ground
18
SRC4#
O, DIF 100 MHz Differential serial reference clocks.
19
SRC4
O, DIF 100 MHz Differential serial reference clocks.
20
VDD
PWR 3.3V power supply
21
SSON
I
3.3V LVTTL input for enabling spread spectrum clock
0 = Disable, 1 = Enable (-0.5% SS)
External 10K ohm pull-up or pull-down resistor required
22
VSS
GND
Ground
23
XOUT
O, SE 14.318 MHz Crystal output.
24
XIN
I
14.318 MHz Crystal input.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SL28SRC04BZIT | 功能描述:時鐘發(fā)生器及支持產品 PCIE Clk Gen 14.318M Xin 2PCIE out Gen3 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28SRC04BZITR | 制造商:Silicon Laboratories Inc 功能描述: |
| SL29041-90TV | 制造商:STEC Inc 功能描述:COSTS NOT CURRENT CALL CMM - Bulk |
| SL29082-90GV | 制造商:STEC Inc 功能描述:REQUIRES QUOTE TO BUY! - Bulk |
| SL295E104MAB | 功能描述:多層陶瓷電容器MLCC - 含引線 50volts 0.1uF 20% Z5U RoHS:否 制造商:AVX 電容:470 pF 容差:10 % 電壓額定值:3 kV 端接類型:Radial 工作溫度范圍: 溫度系數(shù)/代碼:X7R 引線間隔:5.08 mm 產品:Automotive MLCCs 引線類型: |
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