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參數(shù)資料
| 型號： | SL28774ELCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 3/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK CK505 CALPELLA 32QFN |
| 標準包裝： | 2,500 |
| 系列： | EProClock® |
| 類型： | 時鐘/頻率發(fā)生器，多路復用器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務器 |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:8 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 133MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應商設備封裝： | * |
| 包裝： | * |
SL28774
...................... Document #: 001-08400 Rev ** Page 11 of 19
PD# (Power down) Clarification
The CKPWRGD/PD# pin is a dual-function pin. During initial
power up, the pin functions as CKPWRGD. Once CKPWRGD
has been sampled HIGH by the clock chip, the pin assumes
PD# functionality. The PD# pin is an asynchronous active
LOW input used to shut off all clocks cleanly before shutting
off power to the device. This signal is synchronized internally
to the device before powering down the clock synthesizer. PD#
is also an asynchronous input for powering up the system.
When PD# is asserted LOW, clocks are driven to a LOW value
and held before turning off the VCOs and the crystal oscillator.
PD# (Power down) Assertion
When PD# is sampled LOW by two consecutive rising edges
of CPU clocks, all single-ended outputs will be held LOW on
their next HIGH-to-LOW transition and differential clocks must
held LOW. When PD# mode is desired as the initial power on
state, PD# must be asserted LOW in less than 10
s after
asserting CKPWRGD.
PD# Deassertion
The power up latency is less than 1.8 ms. This is the time from
the deassertion of the PD# pin or the ramping of the power
supply until the time that stable clocks are generated from the
clock chip. All differential outputs stopped in a three-state
condition, resulting from are driven high in less than 300
s of
PD# deassertion to a voltage greater than 200 mV. After the
clock chip’s internal PLL is powered up and locked, all outputs
are enabled within a few clock cycles of each clock. Figure 4
is an example showing the relationship of clocks coming up.
Figure 3. Power Down Assertion Timing Waveform
Figure 4. Power Down Deassertion Timing Waveform
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SL28774ELI | 功能描述:時鐘發(fā)生器及支持產品 Shrink CK505 for Calpella platforms RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28774ELIT | 功能描述:時鐘發(fā)生器及支持產品 Shrink CK505 for Calpella platforms RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28779ELC | 功能描述:時鐘發(fā)生器及支持產品 Calpella IrnLk JpFrt Ibex Pk Add USB28748 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28779ELCT | 功能描述:時鐘發(fā)生器及支持產品 Calpella IrnLk JpFrt Ibex Pk Add USB28748 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28779ELI | 功能描述:時鐘發(fā)生器及支持產品 Calpella IrnLk JpFrt Ibex Pk Add USB28748 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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