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參數(shù)資料
| 型號(hào)： | SL28647CLCT |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC72 |
| 封裝： | 10 X 10 MM, ROHS COMPLIANT, QFN-72 |
| 文件頁數(shù)： | 26/27頁 |
| 文件大?。?/td> | 269K |
| 代理商： | SL28647CLCT |
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SL28647
.......................Document #: 001-05103 Rev *B Page 8 of 27
6
0
TEST_MODE
Test Clock Mode Entry Control
0 = Normal operation, 1 = REF/N or Tri-state mode,
5
1
REF1 Bit0
REF1 Slew Rate Control Bit 0, See Table 6 for more detail
0 = Low, 1 = High
4
1
REF0 Bit0
REF0 Slew Rate Control Bit 0, See Table 6 for more detail
0 = Low, 1 = High
3
1
PCI, PCIF and SRC clock
outputs except those set to
free running
SW PCI_STP Function
0 = SW PCI_STP assert, 1= SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
2
HW
FSC
FSC Reflects the value of the FSC pin sampled on power up
0 = FSC was low during CK_PWRGD assertion
1
HW
FSB
FSB Reflects the value of the FSB pin sampled on power up
0 = FSB was low during CK_PWRGD assertion
0
HW
FSA
FSA Reflects the value of the FSA pin sampled on power up
0 = FSA was low during CK_PWRGD assertion
Byte 7 Control Register 7 (continued)
Bit
@Pup
Name
Description
Byte 8 Vendor ID
Bit
@Pup
Name
Description
7
0
Revision Code Bit 3
6
0
Revision Code Bit 2
5
1
Revision Code Bit 1
4
0
Revision Code Bit 0
3
1
Vendor ID Bit 3
2
0
Vendor ID Bit 2
1
0
Vendor ID Bit 1
0
Vendor ID Bit 0
Byte 9 Control Register 9
Bit
@Pup
Name
Description
7
0
RESERVED
6
0
RESERVED
5
0
RESERVED
4
0
RESERVED
3
1
RESERVED
2
1
48M Bit0
48M Slew Rate Control Bit 0, See Table 6 for more detail
0 = Low, 1 = High
1
RESERVED
0
1
PCIF0 Bit0
PCIF0 Slew Rate Control Bit 0, See Table 6 for more detail
0 = Low, 1 = High
Byte 10 Control Register 10
Bit
@Pup
Name
Description
7
0
RESERVED
6
0
RESERVED
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SL28748ELC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Calpella IronLake Jasper Forest IbexPk RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28748ELCT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Calpella IronLake Jasper Forest IbexPk RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28748ELCTR | 制造商:Silicon Laboratories Inc 功能描述: |
| SL28748ELI | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Calpella IronLake Jasper Forest IbexPk RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28748ELIT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Calpella IronLake Jasper Forest IbexPk RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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