參數(shù)資料
型號(hào): SL28610BLC
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 6/23頁(yè)
文件大小: 0K
描述: IC CLK ATOM POULSBO PCIE 48QFN
標(biāo)準(zhǔn)包裝: 490
類型: 時(shí)鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: Intel CPU 服務(wù)器
輸入: 時(shí)鐘,晶體
輸出: HCSL,LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:9
差分 - 輸入:輸出: 無/是
頻率 - 最大: 200MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 85°C
安裝類型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
SL28610
...................... DOC #: SP-AP-0078 (Rev. 1.0) Page 14 of 23
CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable are stopped
within two to six CPU clock periods after sampled by two rising
edges of the internal CPUC clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal causes all stopped
CPU outputs to resume normal operation in a synchronous
manner. No short or stretched clock pulses are produced when
the
clock
resumes.
The
maximum
latency
from
the
deassertion to active outputs is no more than two CPU clock
cycles.
.
Note: *Differential clocks output state can be configured through Byte 19 bits 3:.0
CPU_STP#
CPUT
CPUC
Figure 4. CPU_STP# Assertion Waveform
CPU_STP#
CPUT
CPUC
CPUT Internal
Tdrive_CPU_STP#,10 ns>200 mV
CPUC Internal
Figure 5. CPU_STP# Deassertion Waveform
Table 1. Output Driver Status during PCI_STPPCI_STP# and CPU_STP#
CPU_STP# Asserted
SMBus Disabled
OE# Pins Disabled
Single-ended Clocks
Stoppable
Running
Driven low
Non stoppable
Running
Differential Clocks
Stoppable
Clock driven high
Driven Low
Clock driven high*
Clock# driven low
Clock# driven low*
Non stoppable
Running
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SL28610BLITR 制造商:Silicon Laboratories Inc 功能描述:
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