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參數(shù)資料
| 型號： | SL23EP09ZI-1T |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 4.40 MM, ROHS COMPLIANT, TSSOP-16 |
| 文件頁數(shù)： | 14/14頁 |
| 文件大?。?/td> | 181K |
| 代理商： | SL23EP09ZI-1T |
Rev 2.0, May 12, 2008
Page 9 of 14
SL23EP09
AC Electrical Specifications (VDD=3.3V and 2.5V) (cont.)
Notes:
3. Typical jitter is measured at 3.3V or 2.5V, 30
°C with all outputs driven into the maximum specified load.
Symbol
Description
Condition
Min
Typ
Max
Unit
tPLLOCK
PLL Lock Time[9]
Time from 90% of VDD to valid clocks on all the
output clocks
–
1.0
ms
CCJ
Cycle-to-cycle Jitter
[2,3]
3.3V supply, >66 MHz, <15 pF, high drive
–
30
60
ps
3.3V supply, >66 MHz, <15 pF, standard drive
–
50
185
ps
2.5V supply, >66 MHz, <15 pF, high drive
–
70
150
ps
2.5V supply, >66 MHz, <15 pF, standard drive
–
100
250
ps
3.3V supply, >66 MHz, <30 pF, high drive
–
50
350
ps
3.3V supply, >66 MHz, <30 pF, standard drive
–
65
250
ps
2.5V supply, >66 MHz, <30 pF, high drive
–
75
430
ps
S2:S1 = 1:0 mode, 3.3V, <15pF, high drive
–
15
40
ps
S2:S1 = 1:0 mode, 3.3V, <15pF, standard drive
–
15
40
ps
S2:S1 = 1:0 mode, 2.5V, <15pF, high drive
–
20
50
ps
S2:S1 = 1:0 mode, 2.5V, <15pF, standard drive
–
20
50
ps
PPJ
[2,3]
Peak Period Jitter
3.3V supply, >100 MHz, <15 pF, standard drive
–
40
90
ps
3.3V supply, 66-100 MHz, <15 pF, standard
drive
–
50
95
ps
2.5V supply, 66-100 MHz, <15 pF, high drive
–
40
85
ps
2.5V supply, >66 MHz, <15 pF, standard drive
–
75
180
ps
2.5V supply, >100 MHz, <15 pF, high drive
–
15
45
ps
S2:S1 = 1:0 mode, 3.3V, <15pF, standard drive
–
25
60
ps
S2:S1 = 1:0 mode, 3.3V, <15pF, high drive
–
25
60
ps
S2:S1 = 1:0 mode, 2.5V, <15pF, standard drive
–
40
80
ps
S2:S1 = 1:0 mode, 2.5V, <15pF, high drive
–
40
80
ps
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