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參數(shù)資料
| 型號(hào)： | SL23EP08SI-1 |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, SOIC-16 |
| 文件頁(yè)數(shù)： | 3/15頁(yè) |
| 文件大?。?/td> | 220K |
| 代理商： | SL23EP08SI-1 |
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Rev 1.0, May 18, 2006
Page 11 of 15
SL23EP08
External Components & Design Considerations
Typical Application Schematic
SL23EP08
CL
0.1
μF
0.1
μF
CLKIN
FBK
CLKA1
CLKB4
GND
S1
S2
VDD
1
4
13
9
8
5
12
11
2
16
VDD
CLKA2
3
CL-4pF
Comments and Recommendations
Decoupling Capacitor: A decoupling capacitor of 0
.1μF must be used between VDD and VSS pins. Place the capacitor on
the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to the GND via
should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD pin.
Series Termination Resistor: A series termination resistor is recommended if the distance between the output clocks and
the load is over 1 inch. The nominal impedance of the clock outputs is given on the page 4. Place the series termination
resistors as close to the clock outputs as possible.
Zero Delay and Skew Control: All outputs and CLKIN pins should be loaded with the same load to achieve “Zero Delay”
between the CLKIN and the outputs. The CLKOUT pin is connected to CLKIN internally on-chip for feedback to PLL, and
sees an additional 4 pF load with respect to Bank A and B clocks. For applications requiring zero input/output delay, the load
at the all output pins including the CLKOUT pin must be the same. If any delay adjustment is required, the capacitance at the
CLKOUT pin could be increased or decreased to increase or decrease the delay between Bank A and B clocks and CLKIN.
For minimum pin-to-pin skew, the external load at all the Bank A and B clocks must be the same.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SL23EP09SC-1 | 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| SL23EP09SC-1T | 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| SL23EP09ZI-1HT | 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| SL23EP09SI-1 | 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| SL23EP09ZI-1T | 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SL23EP08SI-1H | 功能描述:時(shí)鐘緩沖器 10-220MHz 8 Out ZDB 3.3V-2.5V Fout=Fin RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| SL23EP08SI-1HT | 功能描述:時(shí)鐘緩沖器 10-220MHz 8 Out ZDB 3.3V-2.5V Fout=Fin RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| SL23EP08SI-1T | 功能描述:時(shí)鐘緩沖器 10-133MHz 8 Out ZDB 3.3-2.5V Fout=Fin RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| SL23EP08SI-2 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB) |
| SL23EP08SI-2T | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB) |
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