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參數(shù)資料
| 型號(hào)： | SL23EP05IT-1 |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, SOIC-8 |
| 文件頁(yè)數(shù)： | 10/11頁(yè) |
| 文件大?。?/td> | 154K |
| 代理商： | SL23EP05IT-1 |
Rev 0.0, September 18, 2006
Page 8 of 11
SL23EP05
External Components & Design Considerations
Typical Application Schematic
SL23EP05
CL
CCLKOUT = CL-4pF
0.1
μF
CLKIN
CLKOUT
CLK1
CLK4
GND
VDD
1
6
4
7
3
8
Comments and Recommendations
Decoupling Capacitor:
A decoupling capacitor of 0.1μF must be used between VDD and VSS on the pins 6 and 4. Place the
capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to the
GND via should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD pin.
Series Termination Resistor: A series termination resistor is recommended if the distance between the output (SSCLK) and
the load is over 1 inch. The nominal impedance of the SSCLK o
utput is about 30 Ω. Use 20 Ω resistor in series with the
output to terminate 50Ω trace impedance and place 20 Ω resistor as close to the clock outputs as possible.
Zero Delay and Skew Control: All outputs and CLKIN pins should be loaded with the same load to achieve “Zero Delay”
between the CLKIN and the outputs. The CLKOUT pin is connected to CLKIN internally on-chip for internal feedback to PLL,
and sees an additional 4 pF load with respect to the clock pins. For applications requiring zero input/output delay, the load at
the all output pins including the CLKOUT pin must be the same. If any delay adjustment is required, the capacitance at the
CLKOUT pin could be increased or decreased to increase or decrease the delay between clocks and CLKIN.
For minimum pin-to-pin skew, the external load at the clocks must be the same.
相關(guān)PDF資料 |
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| SL23EP05SI-1 | 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| SL23EP05SI-1HT | 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| SL23EP05SI-1 | 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| SL23EP05SI-1T | 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| SL23EP08SC-2HT | 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SL23EP05SC-1 | 功能描述:時(shí)鐘緩沖器 10-220MHz 5 Outputs ZDB 3.3-2.5V RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| SL23EP05SC-1H | 功能描述:時(shí)鐘緩沖器 10-220MHz 5 Outputs ZDB 3.3-2.5V Hi Drv RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| SL23EP05SC-1HT | 功能描述:時(shí)鐘緩沖器 10-220MHz 5 Outputs ZDB 3.3-2.5V Hi Drv RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| SL23EP05SC-1T | 功能描述:時(shí)鐘緩沖器 10-220MHz 5 Outputs ZDB 3.3-2.5V RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| SL23EP05SI-1 | 功能描述:時(shí)鐘緩沖器 10-220MHz 5 Outputs ZDB 3.3-2.5V RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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