參數(shù)資料
型號(hào)： SL23EP04NZZC-1Z
廠商： SILICON LABORATORIES
元件分類： 時(shí)鐘及定時(shí)
英文描述： 23EP SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
封裝： 4.40 MM, ROHS COMPLIANT, TSSOP-8
文件頁(yè)數(shù)： 11/11頁(yè)
文件大?。?/td> 175K
代理商： SL23EP04NZZC-1Z
Rev 2.1, May 2, 2008
Page 9 of 11
SL23EP04NZ
Output Duty Cycle
DC3
CL=15pF, Fout=80 MHz
Measured at VDD/2
45
50
55
%
Output Rise/Fall Time
tr/f-1
CL=15pF, measured at 0.6V to 1.7V
–
1.8
ns
Output Rise/Fall Time
tr/f-2
CL=30pF, measured at 0.6V to 1.7V
–
2.4
ns
Output to Output Skew
SKW1
Measured at VDD/2 and
Outputs are equally loaded
–
100
200
ps
Part to Part Skew
SKW2
Measured at VDD/2 and
Outputs are equally loaded
–
120
240
ps
Propagation Delay Time
PDT
Measured at VDD/2 from CLKIN to
Output Clock rising edge and Outputs
are equally loaded
–
4.2
6.8
ns
Cycle-to-Cycle Jitter
CCJ1
CLKIN=66MHz and CL=0 (No Load)
–
70
140
ps
Cycle-to-Cycle Jitter
CCJ2
CLKIN=133MHz and CL=0 (No Load)
–
60
120
ps
Power-up Time
tpu
Power-up time for VDD to reach
minimum specified time
0.05
–
100
ms
External Components & Design Considerations
Typical Application Schematic
SL23EP04NZ
0.1
μF
CLKIN
CLK2
CLK3
GND
VDD
1
6
4
8
5
3
CL
CLK1
CL
CLK4
7
OE
2
Comments and Recommendations
Decoupling Capacitor:
A decoupling capacitor of 0.1μF must be used between VDD and VSS pins. Place the
capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and
to the GND via should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD
pin.
Package Outline and Package Dimensions
相關(guān)PDF資料
PDF描述
SL23EP04NZZI-1Z 23EP SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
SL23EP04NZZI-1T 23EP SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
SL23EP04NZZI-1ZT 23EP SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
SL23EP04SC-1T 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
SL23EP04SI-2HT 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SL23EP04NZZC-1ZT 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Low Jitter and Skew DC to 220 MHz Clock Buffer
SL23EP04NZZI-1 功能描述:時(shí)鐘緩沖器 0-220MHz 4 Outputs NZDB 3.3-2.5V RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
SL23EP04NZZI-1T 功能描述:時(shí)鐘緩沖器 0-220MHz 4 Outputs NZDB 3.3-2.5V RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
SL23EP04NZZI-1Z 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Low Jitter and Skew DC to 220 MHz Clock Buffer
SL23EP04NZZI-1ZT 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Low Jitter and Skew DC to 220 MHz Clock Buffer
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*