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參數(shù)資料
| 型號(hào)： | SL16020DCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 8/10頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CLOCK AMD GRAPHICS 10TDFN |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 系列： | EProClock® |
| 類型： | * |
| PLL： | 帶旁路 |
| 輸入： | 時(shí)鐘，晶體 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 100MHz |
| 除法器/乘法器： | 無(wú)/無(wú) |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 工作溫度： | -10°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
Rev 2.2, August 1, 2010
Page 7 of 10
SL16020DC
External Components and Design Considerations
Typical Application Circuit
SL16020DC
XIN(1)
VDD2(8)
XOUT(10)
SSCLK(5)
SSEL1(3)
SSEL0(7)
100MHz
27MHz
CL1
CL2
0.1
μF
VSS2(2)
REFCLK(9)
27MHz
VSS1(6)
VDD1(4)
10
μF
External crystal and crystal
load capacitors required if
crystal is used.
If external clock (XO) is used
leave Pin-10 XOUT
unconnected (N/C) and drive
Pin 1 XIN/CLKIN with clock
VDD
0.1
μF
5K
This example is configured
for -0.5% Spread
SSEL0=M (VDD/2) and
SSEL1=LOW (VSS)
5K
Figure 4. Typical Application Schematic
Comments and Recommendations
Crystal and Crystal Load: Only use a parallel resonant fundamental AT cut crystal. DO NOT USE higher overtone
crystals. To meet the crystal initial accuracy specification (in ppm) make sure that external crystal load capacitor is
matched to crystal load specification. To determine the value of CL1 and CL2, use the following formula;
C1 = C2 = 2CL – (Cpin + Cp)
Where: CL is load capacitance stated by crystal manufacturer
Cpin is the SL16010 pin capacitance (4pF)
Cp is the parasitic capacitance of the PCB traces.
EXAMPLE; if a crystal with CL=12pF specification is used and Cp=1pF (parasitic PCB capacitance on PCB), 19 or
20pF external capacitors from pins XIN (pin-1) and XOUT (Pin-10) to VSS are required since CXIN=CXOUT=4pF for
the SL1610DC product. Users must verify Cp value.
Decoupling Capacitor: A decoupling ca
pacitor of 0.1μF must be used between VDD1/2 pins and VSS1/2 pin. Place
the capacitor on the component side of the PCB as close to the VDD1/2 pins as possible. The PCB trace to the
VDD1/2 pins and to the VSS via should be kept as short as possible Do not use vias between the decoupling
capacitor and the VDD1/2 pins. In addition, a 10uf capacitor should be placed between VDD and VSS.
Series Termination Resistor: A series termination resistor is recommended if the distance between the outputs
(REFCLK and SSCLK) and the load if PCB trace is over 1 inch. The nominal impedance of the outputs is about 24
Ω. Use 22 Ω resistors in series with the outputs to terminate 50Ω trace impedance and place 22 Ω resistors as close
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