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參數(shù)資料
| 型號： | SL15316ZI-XXXT |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | 0.173 INCH, ROHS COMPLIANT, TSSOP-16 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 276K |
| 代理商： | SL15316ZI-XXXT |
Rev 1.0, August 7, 2008
Page 3 of 12
SL15316
11
SSCLK2 or REFCLK2
or PD#/OE/SSON#/FS
I/O
This pin can be programmed as SSCLK2 or REFCLK2.
12
SSCLK3 or REFCLK3
Output
This pin can be programmed as SSCLK3 or REFCLK3.
13
SSCLK4 or REFCLK4
Output
This pin can be programmed as SSCLK4 or REFCLK4.
14
VSS
Power
Power supply ground.
15
SSCLK5 or REFCLK5
or PD#/OE/SSON#/FS
I/O
This pin can be programmed as SSCLK5 or REFCLK5 or one of
PD#/OE/SSON#/FS functions.
16
VDDO
Power
Positive power supply for pins 12, 13 and 15. can be 3.3V to 2.5V
or 1.8V +/-10% where VDDO≤VDD.
Available REFCLK Frequencies and Dividers
All REFCLK outputs are programmed by using buffered crystal or clock input and output dividers. These
outputs can not be programmed for spread spectrum clock function. The table below gives the available
output dividers for REFCLK outputs:
Pin Number
Pin Name
Description
7
REFCLK1
Crystal or clock input reference frequency divide by 1 to 32
11
REFCLK2
Crystal or clock input reference frequency divide by 1 to 32
12
REFCLK3
Crystal or clock input reference frequency (no divider)
13
REFCLK4
Crystal or clock input reference frequency divide by 2 to 32
15
REFCLK5
Crystal or clock input reference frequency divide by 2N where
N = 2 to 16.
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相關代理商/技術參數(shù) |
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