參數(shù)資料
型號(hào)： SL15300ZI-XXXT
廠商： SILICON LABORATORIES
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： OTHER CLOCK GENERATOR, PDSO8
封裝： 0.173 INCH, ROHS COMPLIANT, TSSOP-8
文件頁(yè)數(shù)： 13/16頁(yè)
文件大?。?/td> 365K
代理商： SL15300ZI-XXXT
Rev 1.0, August 14, 2008
Page 6 of 16
SL15300
Cycle-to-Cycle Jitter
(SSCLK – Pins 4/6/7/8)
CCJ1
FIN=30MHz, all 4 clocks are at
33MHz, +/-2.0% Spread. CL=15pF
-
TBD
ps
Cycle-to-Cycle Jitter
(SSCLK – Pins 4/6/7/8)
CCJ2
FIN=30MHz, all 4 clocks are at
33MHz, +/-2.0% Spread. CL=15pF
-
TBD
ps
Power-down Time
tPD
Time from PD# falling edge to Hi-Z
at outputs (Asynchronous)
-
150
350
ns
Power-up Time
(Crystal or Clock)
tPU
Time from PD# rising edge to valid
frequency at outputs
(Asynchronous)
-
3.5
5.0
ms
Power Supply Ramp
Time
tPSR
Time for VDD reaching minimum
specified value and monolithic
power supply ramp
-
12
ms
Output Enable Time
tOE
Time from OE falling edge to Hi-Z at
outputs (Asynchronous)
-
180
350
ns
Output Disable Time
tOD
Time from OE falling edge to Hi-Z at
outputs (Asynchronous)
-
180
350
ns
Spread Percent Range
SPR-1
Center Spread, SSCLK-1/2/3/4
+/-0.125
-
+/-2.5
%
Spread Percent Range
SPR-2
Down Spread, SSCLK-1/2/3/4
-5.0
-
-0.25
%
Spread Percent Variation
ΔSS%
Variation of programmed Spread %
-15
-
15
%
Modulation Frequency
FMOD
Programmable, 31.5 kHz standard
25
31.5
120
kHz
DC Electrical Characteristics (C-Grade)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70 Deg C
Description
Symbol
Condition
Min
Typ
Max
Unit
Operating Voltage
VDD
VDD+/-10%
2.25
2.5
2.75
V
Input Low Voltage
VIL
CMOS Level, if Pins 4 and 8
programmed as PD#, OE,
SSON# or FS
0
-
0.3VDD
V
Input High Voltage
VIH
CMOS Level, if Pins 4 and 8
programmed as PD#, OE,
SSON# or FS.
0.7VDD
-
VDD
V
Output High Voltage
VOH1
IOH=10mA , If Pins 4, 6, 7 and
8 are programmed as
SSCLK/REFCLK
VDD-0.4
-
V
Output Low Voltage
VOL1
IOL=10mA, If Pins 4, 6, 7 and 8
are programmed as
SSCLK/REFCLK
-
0.4
V
Input High Current
IIH
VIN=VDD, Pins 4 and 8. If
outputs are programmed as
PD#, OE, SSON# or FS and no
pull-up/down resister used
-10
-
10
μA
Input Low Current
IIL
VIN=GND, Pins 4 and 8. If
outputs are programmed as
PD#, OE, SSON# or FS and no
pull-up/down resister used
-10
-
10
μA
相關(guān)PDF資料
PDF描述
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