
SL11R
Document #: 38-08006  Rev. **
Page 3 of 85
Table of Contents
 (continued)
4.9.8  USB Endpoint 0 Count Register (0x0122: R/W) ...............................................................................20
4.9.9  USB Endpoint 1 Count Register (0x0126: R/W) ...............................................................................20
4.9.10  USB Endpoint 2 Count Register (0x012A: R/W) ............................................................................20
4.9.11  USB Endpoint 3 Count Register (0x012E: R/W) .............................................................................21
4.10  Processor Control Registers ....................................................................................................21
4.10.1  Configuration Register (0xC006: R/W) ...........................................................................................21
4.10.2  Speed Control Register (0xC008: R/W) ..........................................................................................22
4.10.3  Power Down Control Register (0xC00A: R/W) ...............................................................................23
4.10.4  Breakpoint Register (0xC014: R/W) ................................................................................................23
4.11  Interrupts ....................................................................................................................................23
4.11.1  Hardware Interrupts .........................................................................................................................24
4.11.2  Interrupt Enable Register (0xC00E: R/W) .......................................................................................24
4.11.3  GPIO Interrupt Control Register (0xC01C: R/W) ............................................................................25
4.11.4  Software Interrupts ...........................................................................................................................25
4.12  UART Interface. ..........................................................................................................................27
4.12.1  UART Control Register (0xC0E0: R/W) ...........................................................................................27
4.12.2  UART Status Register (0xC0E2: Read Only) ..................................................................................28
4.12.3  UART Transmit Data Register (0xC0E4: Write Only) .....................................................................28
4.12.4  UART Receive Data Register (0xC0E4: Read Only) ......................................................................28
4.13  Serial EEPROM Interface (2-wire serial interface) ..................................................................28
4.14  External SRAM, EPROM, DRAM ...............................................................................................29
4.14.1  Memory Control Register (0xC03E: R/W) .......................................................................................30
4.14.2  Extended Memory Control Register (0xC03A: R/W) ......................................................................30
4.14.3  Extended Page 1 Map Register (0xC018: R/W) ..............................................................................30
4.14.4  Extended Page 2 Map Register (0xC01A: R/W) .............................................................................31
4.14.5  DRAM Control Register (0xC038: R/W) ..........................................................................................31
4.14.6  Memory Map ......................................................................................................................................31
4.15  General Timers and Watch Dog Timer .....................................................................................33
4.15.1  Timer 0 Count Register (0xC010: R/W) ...........................................................................................33
4.15.2  Timer 1 Count Register (0xC012: R/W) ...........................................................................................33
4.15.3  Watchdog Timer Count & Control Register (0xC00C: R/W) .........................................................33
4.16  Special GPIO Function for Suspend, Resume and Low-Power modes ................................33
4.17  Programmable Pulse/PWM Interface .......................................................................................34
4.17.1  PWM Control Register (0xC0E6: R/W) ............................................................................................34
4.17.2  PWM Maximum Count Register (0xC0E8: R/W) .............................................................................35
4.17.3  PWM Channel 0 Start Register (0xC0EA: R/W) ..............................................................................35
4.17.4  PWM Channel 0 Stop Register (0xC0EC: R/W) ..............................................................................36
4.17.5  PWM Channel 1 Start Register (0xC0EE: R/W) ..............................................................................36
4.17.6  PWM Channel 1 Stop Register (0xC0F0: R/W) ...............................................................................36
4.17.7  PWM Channel 2 Start Register (0xC0F2: R/W) ...............................................................................36
4.17.8  PWM Channel 2 Stop Register (0xC0F4: R/W) ...............................................................................36
4.17.9  PWM Channel 3 Start Register (0xC0F6: R/W) ...............................................................................36
4.17.10  PWM Channel 3 Stop Register (0xC0F8: R/W) .............................................................................37
4.17.11  PWM Cycle Count Register (0xC0FA: R/W) .................................................................................37
4.18  Fast DMA Mode ..........................................................................................................................37
4.18.1  DMA Control Register (0xC02A: R/W) ............................................................................................37
4.18.2  Low DMA Start Address Register (0xC02C: R/W) .........................................................................37
4.18.3  High DMA Start Address Register (0xC02E: R/W) .........................................................................38
4.18.4  Low DMA Stop Address Register (0xC030: R/W) ..........................................................................38
4.18.5  High DMA Stop Address Register (0xC032: R/W) .........................................................................38