參數(shù)資料
型號: SKY72300-21
廠商: Skyworks Solutions Inc
文件頁數(shù): 16/22頁
文件大?。?/td> 0K
描述: IC SYNTHESIZER 2.1GHZ 28-EPTSSOP
產(chǎn)品目錄繪圖: 28-TSSOP
標(biāo)準(zhǔn)包裝: 1
類型: 分數(shù) N 合成器
PLL:
輸入: 時鐘,晶體
輸出: 時鐘,晶體
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.1GHz
除法器/乘法器: 是/無
電源電壓: 2.7 V ~ 3.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.173",4.40mm 寬)裸露焊盤
供應(yīng)商設(shè)備封裝: 28-TSSOP 裸露焊盤
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 587 (CN2011-ZH PDF)
其它名稱: 863-1076-6
DATA SHEET SKY72300-21 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
101217N Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice September 11, 2009
3
Technical Description
The SKY72300-21 is a fractional-N frequency synthesizer using a
modulation technique. The fractional-N implementation
provides low in-band noise by having a low division ratio and fast
frequency settling time. In addition, the SKY72300-21 provides
arbitrarily fine frequency resolution with a digital word, so that the
frequency synthesizer can be used to compensate for crystal
frequency drift in the RF transceiver.
Serial Interface
The serial interface is a versatile three-wire interface consisting of
three pins: Clock (serial clock), Data (serial input), and CS (chip
select). It enables the SKY72300-21 to operate in a system where
one or multiple masters and slaves are present. To perform a
loopback test at startup and to check the integrity of the board
and processor, the serial data is fed back to the master device
(e.g., a microcontroller or microprocessor unit) through a
programmable multiplexer. This facilitates hardware and software
debugging.
Registers
There are ten 16-bit registers in the SKY72300-21. For more
information, see the Register Descriptions section of this
document.
Main and Auxiliary
Modulators
The fractionality of the SKY72300-21 is accomplished by the use
of a proprietary, configurable 10-bit or 18-bit
modulator for
the main synthesizer and 10-bit
modulator for the auxiliary
synthesizer.
Main and Auxiliary Fractional Units
The SKY72300-21 provides fractionality through the use of main
and auxiliary
modulators. The output from the modulators is
combined with the main and auxiliary divider ratios through their
respective fractional units.
VCO Prescalers
The VCO prescalers provide low-noise signal conditioning of the
VCO signals. They translate from an off-chip, single-ended or
differential signal to an on-chip differential Current Mode Logic
(CML) signal. The SKY72300-21 has independent main and
auxiliary VCO prescalers.
Main and Auxiliary VCO Dividers
The SKY72300-21 provides programmable dividers that control
the CML prescalers and supply the required signals to the charge
pump phase detectors. Programmable divide ratios ranging from
38 to 537 are possible in fractional-N mode and from 32 to 543 in
integer-N mode.
Reference Frequency Oscillator
The SKY72300-21 has a self-contained, low-noise crystal
oscillator. This crystal oscillator is followed by the clock
generation circuitry that generates the required clock for the
programmable reference frequency dividers.
Reference Frequency Dividers
The crystal oscillator signal can be divided by a ratio of 1 to 32 to
create the reference frequencies for the phase detectors. The
SKY72300-21 has both a main and an auxiliary frequency
synthesizer, and provides independently configurable dividers of
the crystal oscillator frequency for both the main and auxiliary
phase detectors. The divide ratios are programmed by the
Reference Frequency Dividers Register.
NOTE: The divided crystal oscillator frequencies (which are the
internal reference frequencies), Fref_main and Fref_aux,
are referred to as reference frequencies throughout this
document.
Phase Detectors and Charge Pumps
The SKY72300-21 uses a separate charge pump phase detector
for each synthesizer which provides a programmable gain, Kd,
from 31.25 to 1000 A/2 radians in 32 steps programmed using
the Phase Detector/Charge Pump Control Register.
Frequency Steering
When programmed for frequency power steering, the SKY72300-
21 has a circuit that helps the loop filter steer the VCO, through
the LD/PSmain signal (pin 9). In this configuration, the LD/PSmain
signal can provide for more rapid acquisition.
When programmed for lock detection, internal frequency steering
is implemented and provides frequency acquisition times
comparable to conventional phase/frequency detectors.
Lock Detection
When programmed for lock detection, the SKY72300-21 provides
an active low, pulsing open collector output using the LD/PSmain
signal (pin 9) to indicate the out-of-lock condition. When locked,
the LD/PSmain signal is tri-stated (high impedance).
Power Down
The SKY72300-21 supports a number of power-down modes
through the serial interface. For more information, see the
Register Descriptions section of this document.
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