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參數(shù)資料
| 型號： | SII161A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SiI 161A PanelLink Receiver |
| 中文描述： | 精工161A條PanelLink接收機 |
| 文件頁數(shù)： | 6/22頁 |
| 文件大?。?/td> | 260K |
| 代理商： | SII161A |
S ilic on Image, Inc .
SiI 161
A
SiI
-DS-0009-D
S ilic on Image, Inc .
6
Subject to Change without Notice
AC Specifications
(continued)
Under normal operating conditions unless otherwise specified.
Symbol
Parameter
R
CIP
ODCK Cycle Time
1
F
CIP
ODCK Frequency
1
R
CIP
ODCK Cycle Time
1
F
CIP
ODCK Frequency
1
R
CIH
ODCK High Time
4
(165MHz, 1-pixel/clock, PIXS = 0)
Conditions
C
L
= 10pF;
ST = 1
C
L
= 5pF;
ST = 0
C
L
= 10pF;
ST = 1
C
L
= 5pF;
ST = 0
Min
6.06
25
12.1
12.5
1.7
Typ
Max Units
40
165
80
82.5
(1-pixel/clock)
(1-pixel/clock)
(2-pixels/clock)
(2-pixels/clock)
ns
MHz
ns
MHz
ns
1.3
ns
R
CIL
ODCK Low Time
4
(165MHz, 1-pixel/clock, PIXS = 0)
2.0
ns
1.4
ns
T
PDL
T
HSC
T
FSC
Delay from PD Low to high impedance outputs
1
Link disabled (DE inactive) to SCDT low
1
Link disabled (Tx power down) to SCDT low
5
Link enabled (DE active) to SCDT high
1
100
25
10
250
40
ns
ms
ms
DE
edges
R
CIP
T
ST
ODCK high to even data output
1
1
Guaranteed by design.
2
Jitter defined as per DVI 1.0 Specification, Section 4.6
Jitter Specification
.
3
Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7
Electrical Measurement Procedures
.
4
Output clock duty cycle is independent of the differential input clock duty cycle and the IDCK duty cycle.
5
Measured when transmitter was powered down (see Si
I
/AN-0005 “
PanelLink Basic Design/Application Guide
,” Section 2.4).
0.25
Notes:
Setup and Hold Timings for data rates other than 165 MHz:
The measurements shown above are minimum setup and hold timings based on the maximum data rate of 165 MHz.
To estimate the setup and hold times for slower data rates (for either different resolutions or 2 pixel per clock mode),
the following formula can be used:
Time (at new frequency) = Time (165 MHz) + (Clock Period at new frequency – Clock Period at 165 MHz)/2
For the case of high strength output (ST=1) with a 10 pf load, and using the standard ODCK (ODCK_INV = 0), the
table below shows the minimum set up and hold times for other speeds as follows:
Data Rate (MHz)
165
112
82.5
56
Clock (ns) Setup (ns) Hold (ns)
6.06
0.70
8.93
2.13
12.12
3.73
17.86
6.60
3.80
5.23
6.83
9.70
UXGA 1 pixel/clock
SXGA 1 pixel/clock
UXGA 2 pixels/clock
SXGA 2 pixels/clock
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