參數(shù)資料
型號: SI824XCLASSD-KIT
廠商: Silicon Laboratories Inc
文件頁數(shù): 14/30頁
文件大小: 0K
描述: BOARD EVAL FOR SI824X
標準包裝: 1
放大器類型: D 類
輸出類型: 2 通道(立體聲)
在某負載時最大輸出功率 x 通道數(shù)量: 120W x 2 @ 8 歐姆
板類型: 完全填充
已用 IC / 零件: Si824x
已供物品:
其它名稱: 336-2002
Si824x
Rev. 1.0
21
3.7.3. Undervoltage Lockout (UVLO)
The UVLO circuit unconditionally drives VO low when VDD is below the lockout threshold. Referring to Figures 35
and 36, upon power up, the Si824x is maintained in UVLO until VDD rises above VDDUV+. During power down, the
Si824x enters UVLO when VDD falls below the UVLO threshold plus hysteresis (i.e., VDD < VDDUV+ – VDDHYS).
Figure 35. Si824x UVLO Response (8 V)
Figure 36. Si824x UVLO Response (10 V)
3.7.4. Control Inputs
PWM inputs are high-true, TTL level-compatible logic inputs. VOA is high and VOB is low when the PWM input is
high, and VOA is low and VOB is high when the PWM input is low.
3.7.5. Disable Input
When brought high, the DISABLE input unconditionally drives VOA and VOB low regardless of the states of input.
Device operation terminates within tSD after DISABLE = VIH and resumes within tRESTART after DISABLE = VIL.
The DISABLE input has no effect if VDDI is below its UVLO level (i.e. VOA, VOB remain low). The DISABLE input
is typically connected to external protection circuitry to unconditionally halt driver operation in the event of a fault.
6.0
10
.5
VDDUV+ (Typ)
O
ut
p
u
tV
o
lt
ag
e
(V
O
)
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
Supply Voltage (VDD - VSS) (V)
8.5
10
.5
VDDUV+ (Typ)
O
ut
p
u
tVo
lt
ag
e
(V
O
)
9.0
9.5
10.0 10.5
11.0 11.5 12.0 12.5
Supply Voltage (VDD - VSS) (V)
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