
Si570/Si571
Rev. 0.3
21
7. Ordering Information
The Si570/Si571 supports a wide variety of options including frequency range, start-up frequency, temperature
stability, tuning slope, output format, and V
DD
. Specific device configurations are programmed into the Si570/Si571
at time of shipment. Configurations are specified using the Part Number Configuration chart shown below. Silicon
Labs provides a web browser-based part number configuration utility to simplify this process. Refer to
www.silabs.com/VCXOPartNumber
to access this tool and for further ordering instructions. The Si570/Si571 XO/
VCXO series is supplied in an industry-standard, RoHS compliant, Pb-free, 8-pad, 5 x 7 mm package. Tape and
reel packaging is an ordering option.
Figure 4. Part Number Convention
570 Programmable
XO Product Family
57x
X
1
st
Option Code
V
DD
3.3
3.3
3.3
3.3
2.5
2.5
2.5
2.5
1.8
1.8
3.3
3.3
3.3
3.3
2.5
2.5
2.5
2.5
1.8
1.8
Output Format Output Enable Polarity
LVPECL
LVDS
CMOS
CML
LVPECL
LVDS
CMOS
CML
CMOS
CML
LVPECL
LVDS
CMOS
CML
LVPECL
LVDS
CMOS
CML
CMOS
CML
A
B
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
T
U
V
W
High
High
High
High
High
High
High
High
High
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Note:
CMOS available to 160 MHz.
571 Programmable
VCXO Product Family
R = Tape & Reel
Blank = Trays
Operating Temp Range (°C)
G
–40 to +85 °C
Device Revision Letter
X
D
G
R
Six-Digit Start-up Frequency/I
2
C Address Designator
The Si57x supports a user-defined start-up frequency within the following
bands of frequencies: 10–945 MHz, 970–1134 MHz, and 1213–1417 MHz.
The start-up frequency must be in the same frequency range as that
specified by the Frequency Grade 3
option code.
The Si57x supports a user-defined I
2
C 7-bit address. Each unique start-up
frequency/I
C address combination is assigned a six-digit numerical code.
This code can be requested during the part number request process. Refer
to www.silabs.com/VCXOPartNumber to request an Si57x part number.
X
XXX XXX
3
rd
Option Code
Frequency Grade
Code Frequency Range Supported (MHz)
A
10-945, 970-1134, 1213-1417.5
B
10-810
C
10-215
2
nd
Option Code
Temperature
Stability
± ppm (max)
100
100
50
50
20
50
Tuning Slope
Kv
ppm/V (typ)
180
90
180
90
45
135
Minimum APR
(±ppm) for VDD @
2.5 V
75
Note 6
125
30
Note 6
75
Code
A
B
C
D
E
F
G 20 356 375 300 235
H 20 180 185 145 105
J 20 135 130 104 70
K 100 356 295 220 155
M 20 33 12 Note 6 Note 6
Notes:
1. For best jitter and phase noise performance, always choose the smallest Kv that meets
the application’s minimum APR requirements. Unlike SAW-based solutions which
require higher higher Kv values to account for their higher temperature dependence,
the Si55x series provides lower Kv options to minimize noise coupling and jitter in real-
world PLL designs. See AN255 and AN266 for more information.
2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an
APR of ±25 ppm is able to lock to a clock with a ±25 ppm stability over 15 years over all
operating conditions.
3. Nominal Pull range (±) = 0.5 x V
DD
x tuning slope.
4. Nominal Absolute Pull Range (
±
APR) = Pull range – stability – lifetime aging
= 0.5 x V
DD
x tuning slope – stability – 10 ppm
5. Minimum APR values noted above include worst case values for all parameters.
6. Combination not available.
3.3 V
100
30
150
80
25
100
1.8 V
25
Note 6
75
25
Note 6
50
Si570
Si571
2
nd
Option Code
Code
A
B
Temperature Stability (ppm, max, ±) Total Stablility (ppm, max, ±)
50 61.5
20 31.5