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參數(shù)資料
| 型號(hào)： | SI5365-C-GQ |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 10/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK MULTIPLIER PROG 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | DSPLL® |
| 類型： | 時(shí)鐘乘法器 |
| PLL： | 是 |
| 輸入： | 時(shí)鐘 |
| 輸出： | CML，CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:5 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.05GHz |
| 除法器/乘法器： | 無(wú)/是 |
| 電源電壓： | 1.71 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
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Si5365
18
Rev. 0.5
60
61
BWSEL0
BWSEL1
I
3-Level
Bandwidth Select.
These pins are three level inputs that select the DSPLL closed loop
bandwidth according to the Any-Frequency Precision Clock Family Ref-
erence Manual.
These pins have both weak pullups and weak pulldowns and default to
M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
66
67
DIV34_0
DIV34_1
I
3-Level
CKOUT3 and CKOUT4 Divider Control.
These pins control the division of CKOUT3 and CKOUT4 relative to the
CKOUT2 output frequency. Detailed operations and timing characteris-
tics for these pins may be found in the Any-Frequency Precision Clock
Family Reference Manual.
These pins have both weak pullups and weak pulldowns and default to
M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
68
69
70
71
FRQSEL0
FRQSEL1
FRQSEL2
FRQSEL3
I
3-Level
Multiplier Select.
These pins are three level inputs that select the input clock and clock
multiplication setting according to the Any-Frequency Precision Clock
Family Reference Manual, depending on the FRQTBL setting.
These pins have both weak pullups and weak pulldowns and default to
M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
77
78
CKOUT3+
CKOUT3–
OMULTI
Clock Output 3.
Differential output clock with a frequency specified by FRQSEL and
FRQTBL settings. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive identical
single-ended clock outputs.
Table 6. Si5365 Pin Descriptions (Continued)
Pin #
Pin Name
I/O Signal Level
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SI5366-C-GQ | IC CLOCK MULTIPLIER PREC 100TQFP |
| SI5367A-C-GQ | IC CLOCK MULTIPLIER PROG 100TQFP |
| SI5368A-C-GQ | IC CLK MULTIPLIER ATTEN 100TQFP |
| SI5369A-C-GQ | IC CLK MULT JITTER ATTEN 100TQFP |
| SI5374B-A-GL | IC CLK GEN/JITTER ATTEN 80LBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5365-C-GQR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Pin-Progrm Precision Clk Xplier 4In/5Out RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5365-EVB | 制造商:Silicon Laboratories Inc 功能描述: |
| SI5366 | 制造商:SILABS 制造商全稱:SILABS 功能描述:PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR |
| Si5366-B-GQ | 功能描述:鎖相環(huán) - PLL PIN-PROGRAM CLK MULT /JITTER ATTEN 5 OUT RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| SI5366-B-GQR | 制造商:Silicon Laboratories Inc 功能描述: |
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