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參數(shù)資料
| 型號： | SI5364-H-BL |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 21/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK MULT SONET/SDH 99-PBGA |
| 標(biāo)準(zhǔn)包裝： | 168 |
| 系列： | DSPLL® |
| 類型： | 時(shí)鐘發(fā)生器，扇出緩沖器（分配） |
| PLL： | 是 |
| 輸入： | 時(shí)鐘 |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 675MHz |
| 除法器/乘法器： | 無/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -20°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 99-LBGA |
| 供應(yīng)商設(shè)備封裝： | 99-BGA（11x11） |
| 包裝： | 托盤 |
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Si5364
28
Rev. 2.5
A9
F_ACTV
O
LVTTL
REF/CLKIN_F is Active.
Active high output indicates that REF/CLKIN_F is
selected as the clock input to the DSPLL.
The DH_ACTV output takes precedence over this
signal as an indicator of the DSPLL clock input sta-
tus. When this output is high and the DH_ACTV out-
put is low, REF/CLKIN_F is being used by the
DSPLL to generate the SONET/SDH compatible out-
put clocks. When this output is high and the
DH_ACTV output is high, REF/CLKIN_F is selected,
but the DSPLL is in digital hold mode. Refer to
DH_ACTV.
A10
DH_ACTV
O
LVTTL
Digital Hold Mode Active.
Active high output indicates that the DSPLL is in
digital hold mode. Digital hold mode locks the current
state of the DSPLL and forces the DSPLL to
continue generation of the output clocks with no
additional phase or frequency information from the
input clocks.
C10
RVRT
I*
LVTTL
Revertive Switching.
Selects the revertive switching mode during auto-
matic switching operation. If this input is high during
automatic switching, the revertive switching mode is
selected. The highest priority reference source that is
valid is selected as the DSPLL reference source.
See AUTOSEL pin description. During manual mode
of operation, this input has no effect.
K2
RSTN/CAL
I*
LVTTL
Reset/Calibrate.
When low, the internal circuitry enters the reset mode
and all LVTTL outputs are forced into a high-imped-
ance state. Also, the CLKOUT_n+ and CLKOUT_n–
pins are forced to a nominal CML logic LOW and
HIGH respectively. The FRQSEL_n[1:0] setting must
be set to 01, 10, or 11 to enable this mode. This
mode is useful for in-circuit test applications.
A low-to-high transition on RSTN/CAL initializes all
digital logic to a known condition, enables the device
outputs, and initiates self-calibration of the DSPLL.
At the completion of self-calibration, the DSPLL
begins to lock to the selected clock input signal.
Table 10. Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
*Note:
The LVTTL inputs on the Si5364 device have an internal pulldown mechanism that causes the input to default to a logic
low state if the input is not driven from an external source.
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| Si5364-H-BLR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Precision 19MHz 155MHz 622MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5364-H-GL | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Prcsn Port Card Clock Multiplr RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5364-H-GLR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Precision 19MHz 155MHz 622MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5365 | 制造商:SILABS 制造商全稱:SILABS 功能描述:PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER |
| Si5365/66-EVB | 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Si5365/Si5366 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
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