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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | SI5319C-C-GMR |
| 寤犲晢锛� | Silicon Laboratories Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 2/50闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC CLOCK MULT/ATTENUATOR 36QFN |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 250 |
| 绯诲垪锛� | DSPLL® |
| 椤炲瀷锛� | 鏅傞悩/闋荤巼鍊嶅鍣�锛屾姈鍕曡“娓涘櫒锛屽璺京(f霉)鐢ㄥ櫒 |
| PLL锛� | 鏄� |
| 涓昏鐩殑锛� | 浠ュお缍�(w菐ng)锛孲ONET/SDH |
| 杓稿叆锛� | 鏅傞悩锛屾櫠楂� |
| 杓稿嚭锛� | CML锛孋MOS锛孡VDS锛孡VPECL |
| 闆昏矾鏁�(sh霉)锛� | 1 |
| 姣旂巼 - 杓稿叆:杓稿嚭锛� | 1:1 |
| 宸垎 - 杓稿叆:杓稿嚭锛� | 鏄�/鏄� |
| 闋荤巼 - 鏈€澶э細 | 346MHz |
| 闆绘簮闆诲锛� | 1.71 V ~ 3.63 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 36-VFQFN 瑁搁湶鐒婄洡 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 36-QFN锛�6x6锛� |
| 鍖呰锛� | 甯跺嵎 (TR) |
绗�1闋�鐣�(d膩ng)鍓嶇2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�
Si5319
10
Rev. 1.0
Input Duty Cycle
(Minimum Pulse
Width)
CKNDC
Whichever is smaller
(i.e., the 40% / 60%
limitation applies only
to high-frequency
clocks)
40
鈥�
60
%
2鈥�
鈥�
ns
Input Capacitance
CKNCIN
鈥斺€�
3
pF
Input Rise/Fall Time
CKNTRF
20鈥�80%
See Figure 2
鈥斺€�
11
ns
CKOUT Output Pins
(See ordering section for speed grade vs frequency limits)
Output Frequency
(Output not config-
ured for CMOS or
Disabled)
CKOF
N1
6
0.002
鈥�
945
MHz
N1 = 5
970
鈥�
1134
MHz
N1 = 4
1.213
鈥�
1.4
GHz
Maximum Output
Frequency in CMOS
Format
CKOF
鈥�
212.5
MHz
Output Rise/Fall
(20鈥�80 %) @
622.08 MHz output
CKOTRF
Output not configured for
CMOS or Disabled
See Figure 2
鈥�230
350
ps
Output Rise/Fall
(20鈥�80%) @
212.5 MHz output
CKOTRF
CMOS Output
VDD =1.71
CLOAD =5 pF
鈥斺€�
8
ns
Output Rise/Fall
(20鈥�80%) @
212.5 MHz output
CKOTRF
CMOS Output
VDD =2.97
CLOAD =5 pF
鈥斺€�
2
ns
Output Duty Cycle
Uncertainty @
622.08 MHz
CKODC
100
Load
Line-to-Line
Measured at 50% Point
(Not for CMOS)
鈥斺€�
+/-40
LVCMOS Input Pins
Minimum Reset Pulse
Width
tRSTMN
1鈥�
鈥�
s
Reset to Microproces-
sor Access Ready
tREADY
鈥斺€�
10
ms
Input Capacitance
Cin
鈥斺€�
3
pF
Table 4. AC Specifications (Continued)
(VDD = 1.8 卤 5%, 2.5 卤10%, or 3.3 V 卤10%, TA = 鈥�40 to 85 掳C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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| Si5319-EVB | 鍔熻兘鎻忚堪:鏅傞悩鍜屽畾鏅傚櫒闁嬬櫦(f膩)宸ュ叿 Si5319 Eval Board RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鐢�(ch菐n)鍝�:Evaluation Modules 椤炲瀷:Clock Conditioners 宸ュ叿鐢ㄤ簬瑭曚及:LMK04100B 闋荤巼:122.8 MHz 宸ヤ綔闆绘簮闆诲:3.3 V |
| SI532 | 鍒堕€犲晢:SILABS 鍒堕€犲晢鍏ㄧū:SILABS 鍔熻兘鎻忚堪:DUAL FREQUENCY XO (10 MHZ TO 1.4 GHZ) |
| SI5320 | 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:SONET/SDH PRECISION CLOCK MULTIPLIER IC |
| SI5320BC | 鍒堕€犲晢:SILICON 鍔熻兘鎻忚堪: |
| SI5320-EVB | 鍔熻兘鎻忚堪:鏅傞悩鍜屽畾鏅傚櫒闁嬬櫦(f膩)宸ュ叿 19MHz 155MHz 622MHz Output 15/14 Scaling RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鐢�(ch菐n)鍝�:Evaluation Modules 椤炲瀷:Clock Conditioners 宸ュ叿鐢ㄤ簬瑭曚及:LMK04100B 闋荤巼:122.8 MHz 宸ヤ綔闆绘簮闆诲:3.3 V |
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