參數(shù)資料
型號(hào)： SI5317B-C-GM
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 16/46頁(yè)
文件大?。?/td> 0K
描述： IC CLK JITTER CLEANR PROG 36QFN
應(yīng)用說(shuō)明： SI5315/17 Crystal Selection AppNote
特色產(chǎn)品： Si5317 Jitter Cleaning Clock
標(biāo)準(zhǔn)包裝： 490
系列： DSPLL®
類型： 抖動(dòng)消除器
PLL： 帶旁路
輸入： 時(shí)鐘，晶體
輸出： CML，CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 350MHz
除法器/乘法器： 無(wú)/無(wú)
電源電壓： 1.71 V ~ 3.63 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 36-QFN（6x6）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 628 (CN2011-ZH PDF)
其它名稱： 336-1922
Si5317
Rev. 1.1
23
3.4. Alarms
Summary alarms are available to indicate the overall status of the input signals. Alarm outputs stay high until all
the alarm conditions for that alarm output are cleared.
3.4.1. Loss-of-Signal
The device has loss-of-signal circuitry that continuously monitors CKIN for missing pulses.
An LOS condition on CKIN causes the LOS alarm to become active. Once a LOS alarm is asserted, it remains
asserted until the input clock is validated over a designated time period. The time to clear LOS after a valid input
clock appears is listed in Table 4, “AC Characteristics”. If another error condition on the same input clock is
detected during the validation time, then the alarm remains asserted and the validation time starts over.
3.4.1.1. LOS Algorithm
The LOS circuitry divides down each input clock to produce an 8 kHz to 2 MHz signal. The LOS circuitry
oversamples this divided down input clock using a 40 MHz clock to search for extended periods of time without
input clock transitions. If the LOS monitor detects twice the normal number of samples without a clock edge, a
LOS alarm is declared. Table 4, “AC Characteristics” gives the minimum and maximum amount of time for the
LOS monitor to trigger.
3.4.1.2. Lock Detect
The PLL lock detection algorithm indicates the lock status on the LOL output pin. The algorithm works by
continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. If the time
between two consecutive phase cycle slips is greater than the retrigger time, the PLL is in lock. The LOL output
has a guaranteed minimum pulse width as shown in Table 4, “AC Characteristics”. The LOL pin is also held in the
active state during an internal PLL calibration. The retrigger time is automatically set based on the PLL closed loop
bandwidth (see Table 10).
3.5. VCO Freeze
The Si5317 device features a VCO freeze mode whereby the DSPLL is locked to a frequency value.
If an LOS condition exists on the selected input clock, the device freezes the VCO. In this mode, the device
provides a stable output frequency until the input clock returns and is validated. When the device enters VCO
freeze, the internal oscillator is initially held to its last frequency value.
3.5.1. Recovery from VCO Freeze
When the input clock signal returns, the device transitions from VCO freeze to the selected input clock.
Table 10. Lock Detect Retrigger Time
PLL Bandwidth Setting (BW)
Retrigger Time (ms)
60–120 Hz
53
120–240 Hz
26.5
240–480 Hz
13.3
480–960 Hz
6.6
960–1920 Hz
3.3
1920–3840 Hz
1.66
3840–7680 Hz
0.833
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參數(shù)描述
SI5317B-C-GMR 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Pin-Program Jitter Clean Clk 1In/2Out RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
Si5317C-C-GM 功能描述:標(biāo)準(zhǔn)時(shí)鐘振蕩器 Pin-Program. Jitter Cleaning Clock RoHS:否 制造商:AVX 產(chǎn)品:Standard Clock Oscillators 封裝 / 箱體:7 mm x 5 mm 頻率:75 MHz 頻率穩(wěn)定性:50 PPM 電源電壓:2.5 V 負(fù)載電容: 端接類型:SMD/SMT 最小工作溫度:0 C 最大工作溫度:+ 70 C 輸出格式:LVDS 尺寸: 封裝:Reel 系列:
SI5317C-C-GMR 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Pin-Program Jitter Clean Clk 1In/2Out RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
Si5317D-C-GM 功能描述:標(biāo)準(zhǔn)時(shí)鐘振蕩器 Pin-Program. Jitter Cleaning Clock RoHS:否 制造商:AVX 產(chǎn)品:Standard Clock Oscillators 封裝 / 箱體:7 mm x 5 mm 頻率:75 MHz 頻率穩(wěn)定性:50 PPM 電源電壓:2.5 V 負(fù)載電容: 端接類型:SMD/SMT 最小工作溫度:0 C 最大工作溫度:+ 70 C 輸出格式:LVDS 尺寸: 封裝:Reel 系列:
SI5317D-C-GMR 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Pin-Program Jitter Clean Clk 1In/2Out RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
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