參數(shù)資料
型號(hào)： SI5316-B-GM
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 10/26頁(yè)
文件大小： 0K
描述： IC PREC JITTER ATTENUATOR 36QFN
標(biāo)準(zhǔn)包裝： 50
系列： DSPLL®
類(lèi)型： 時(shí)鐘振動(dòng)衰減器
PLL： 帶旁路
輸入： 時(shí)鐘
輸出： CML，CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 710MHz
除法器/乘法器： 是/無(wú)
電源電壓： 1.62 V ~ 3.63 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 36-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 36-QFN（6x6）
包裝： 管件
Si5316
18
Rev. 1.0
21
CS
I
LVCMOS
Input Clock Select.
This pin functions as the input clock selector. This input is internally
deglitched to prevent inadvertent clock switching during changes in
the CKSEL input state.
0 = Select CKIN1
1 = Select CKIN2
Must be driven high or low.
23
22
BWSEL1
BWSEL0
I
3-Level*
Bandwidth Select.
Three level inputs that select the DSPLL closed loop bandwidth.
Detailed operations and timing characteristics for these pins may be
found in the Any-Frequency Precision Clock Family Reference Man-
ual.
These pins are both pull-ups and pull-downs and default to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
25
24
FRQSEL
1
FRQSEL
0
I
3-Level*
Frequency Select.
Sets the output frequency of the device. When the frequency of
CKIN1 is not equal to CKIN2, the lower frequency input clock must
be equal to the output clock frequency. These pins have both weak
pull-ups and weak pull-downs and default to M. For the pin settings,
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
26
CK1DIV
I
3-Level*
Input Clock 1 Pre-Divider Select.
Pre-divider on CKIN1. Used with CK2DIV to divide input clock
frequencies to a common value.
L = CKIN1 input divider set to 1.
M = CKIN1 input divider set to 4.
H = CKIN1 input divider set to 32.
This pin has a weak pull-up and weak pull-down and defaults to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
27
CK2DIV
I
3-Level*
Input Clock 2 Pre-Divider Select.
Pre-divider on CKIN2. Used with CK1DIV to divide input clock
frequencies to a common value.
L = CKIN2 input divider set to 1.
M = CKIN2 input divider set to 4.
H = CKIN2 input divider set to 32.
This pin has a weak pull-up and weak pull-down and defaults to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
Table 8. Si5316 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
*Note: Denotes 3-Level input pin with states designated as L (ground), M (VDD/2), and H (VDD).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SI5316-B-GMR 制造商:Silicon Laboratories Inc 功能描述:PRECISION CLOCK JITTER ATTENUATOR, 1 OUTPUT - Tape and Reel
Si5316-C-GM 功能描述:鎖相環(huán) - PLL Precsn Clock Jittr Attenuatr 1 Output RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
SI5316-C-GMR 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Pin-Ctrl Precision Jitt Attn 2In/1Out RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
Si5316-EVB 功能描述:時(shí)鐘和定時(shí)器開(kāi)發(fā)工具 Si5316 EVALUATION BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類(lèi)型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
SI5317 制造商:SILABS 制造商全稱(chēng):SILABS 功能描述:Pin-Controlled 1_710 MHz Jitter Cleaning Clock
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