VDD Supply Supply. The device operates from a 1.8, 2.5, or 3.3 V supply. By" />
參數(shù)資料
型號: SI5315A-C-GMR
廠商: Silicon Laboratories Inc
文件頁數(shù): 39/54頁
文件大?。?/td> 0K
描述: IC CLK MULT 8KHZ-644.53MHZ 36QFN
應用說明: SI5315/17 Crystal Selection AppNote
標準包裝: 250
系列: DSPLL®
類型: 時鐘/頻率倍增器,抖動衰減器,多路復用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH/PDH,電信
輸入: CML,CMOS,LVDS,LVPECL
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 644.53MHz
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應商設備封裝: 36-QFN(6x6)
包裝: 帶卷 (TR)
Si5315
44
Rev. 1.0
5, 10,
32
VDD
Supply
Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass
capacitors should be associated with the following VDD pins:
5
0.1 F
10
0.1 F
32
0.1 F
A 1.0 F should also be placed as close to device as is prac-
tical.
7
6
XB
XA
IAnalog
External Crystal or Reference Clock.
External crystal should be connected to these pins to use
internal oscillator based reference. Crystal or reference clock
selection is set by the XTAL/CLOCK pin.
8,
15,19,
20,31
GND
Supply
Ground.
Must be connected to system ground. Minimize the ground
path impedance for optimal performance of this device.
9
AUTOSEL
I
3-Level
Manual/Automatic Clock Selection.
Three level input that selects the method of input clock selec-
tion to be used.
L = Manual
M = Automatic non-revertive
H = Automatic revertive
This pin has a weak pull-up and weak pull-down and defaults
to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
11
XTAL/CLOCK
I
3-Level
External Crystal or Reference Clock Rate.
Three level input that selects the type and rate of external
crystal or reference clock to be applied to the XA/XB port.
This pin has both a weak pull-up and a weak pull-down and
defaults to M.
L = Crystal
M = Clock (Default)
H = Reserved
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
12
13
CKIN2+
CKIN2–
I
Clock Input 2.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency selected from a table of
values. The same frequency must be applied to CKIN1 and
CKIN2.
Table 19. Si5315 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
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相關代理商/技術參數(shù)
參數(shù)描述
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