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參數(shù)資料
| 型號： | SI5110-H-GL |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 5/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX SONET/SDH LP HS 99LFBGA |
| 標(biāo)準(zhǔn)包裝： | 168 |
| 系列： | SiPHY™ |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | SONET/SDH |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 99-LBGA |
| 供應(yīng)商設(shè)備封裝： | 99-BGA（11x11） |
| 包裝： | 托盤 |
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Si5110
Rev. 1.5
13
4. Functional Description
The Si5110 transceiver is a low-power, fully-integrated
serializer/deserializer that provides significant margin to
all
SONET/SDH
jitter
specifications.
The
device
operates from 2.4–2.7 Gbps making it suitable for OC-
48/STM-16
applications,
and
OC-48/STM-16
applications that use 255/238 or 255/237 forward error
correction
(FEC)
coding.
The
low-speed
receive/transmit interface uses a low-power parallel
LVDS interface.
5. Receiver
The receiver within the Si5110 includes a precision
limiting
amplifier,
a
jitter-tolerant
clock
and
data
recovery
unit
(CDR),
and
1:4
demultiplexer.
Programmable data slicing level and sampling phase
adjustment are provided to support bit-error-rate (BER)
optimization for long haul applications.
5.1. Receiver Differential Input Circuitry
The receiver serial input provides proper termination
and biasing through two resistor dividers internal to the
device. The active circuitry has high-impedance inputs
and provides sufficient gain for the clock and data
recovery unit to recover the serial data. The input bias
levels are optimized for jitter tolerance and input
sensitivity and are typically not dc compatible with
standard I/Os; simply ac couple the data lines as shown
in Figure 10.
5.2. Limiting Amplifier
The Si5110 incorporates a limiting amplifier with
sufficient
gain
to
directly
accept
the
output
of
transimpedance amplifiers.
The limiting amplifier provides sufficient gain to fully
saturate with input signals that are greater than 30 mV
peak-to-peak differential. In addition, input signals up to
2 V
peak-to-peak
differential
do
not
cause
any
performance degradation.
5.2.1. Receiver Signal Amplitude Monitoring
The Si5110 limiting amplifier includes circuitry that
monitors the amplitude of the receiver differential input
signal (RXDIN). The RXAMPMON output provides an
analog output signal that is proportional to the input
signal
amplitude.
The
signal
is
enabled
when
SLICEMODE
is
asserted.
The
voltage
on
the
RXAMPMON output is nominally equal to one-half of
the differential peak-to-peak signal amplitude of RXDIN
as shown in Equation 1.
Equation 1
The receiver signal amplitude monitoring circuit is also
used in the generation of the loss-of-signal alarm (LOS).
5.2.2. Loss-of-Signal Alarm (LOS)
The Si5110 can be configured to activate a loss-of-
signal alarm output (LOS) when the RXDIN input
amplitude drops below a programmable threshold level.
An appropriate level of hysteresis prevents unnecessary
switching on LOS.
The LOS threshold level is set by applying a dc voltage
to the LOSLVL input. The mapping of the voltage on the
LOSLVL pin to the LOS threshold level depends on the
state of the SLICEMODE input. (The SLICEMODE input
is used to select either Absolute Slice mode or
Proportional Slice mode operation.)
The
LOSLVL
mapping
for
Absolute
Slice
Mode
(SLICEMODE = 0) is given in Figure 4 on page 15. The
linear region of the assert can be approximated by the
following equation:
Equation 2
where VLOS is the differential pk-pk LOS threshold
referred to the RXDIN input, and VLOSLVL is the voltage
applied to the LOSLVL pin. The linear region of the de-
assert curve can be approximated by the following
equation:
Equation 3
The LOSLVL mapping for Proportional Slice mode
(SLICEMODE = 1) is given in Figure 5 on page 16. The
linear region of the assert can be approximated by the
following equation:
Equation 4
where VLOS is the differential pk-pk LOS threshold
referred to the RXDIN input, and VLOSLVL is the voltage
applied to the LOSLVL pin.
The
linear
region
of
the
assert
curve
can
be
approximated be the following equation:
Equation 5
V
RXAMPMON
V
RXDIN PP
.566
V
LOS
V
LOSLVL
0.958
V
LOS
V
LOSLVL
0.762
V
LOS
V
LOSLVL
0.61
V
LOS
V
LOSLVL
0.72
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