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參數(shù)資料
| 型號： | SI5020-B-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 4/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK DATA REC SONET/SDH 20-QFN |
| 標(biāo)準(zhǔn)包裝： | 75 |
| 系列： | SiPHY™, DSPLL® |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR） |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，ATM 應(yīng)用 |
| 輸入： | 時鐘 |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-QFN（4x4） |
| 包裝： | 管件 |
Si5020
12
Rev. 1.5
4.5. Forward Error Correction (FEC)
The Si5020 supports FEC in SONET OC-48 (SDH
STM-16) applications for data rates up to 2.7 Gbps. In
FEC applications, the appropriate reference clock
frequency is determined by dividing the input data rate
by 16, 32, or 128. For example, if an FEC code is used
that produces a 2.70 Gbps data rate, the required
reference clock would be 168.75, 84.375, or 21.09 MHz.
4.6. Lock Detect
The Si5020 provides lock-detect circuitry that indicates
whether the PLL has achieved frequency lock with the
incoming data. The circuit compares the frequency of a
divided-down version of the recovered clock with the
frequency of the applied reference clock (REFCLK). If
the recovered clock frequency deviates from that of the
reference clock by the amount specified in Table 4 on
page 7, the PLL is declared out-of-lock, and the loss-of-
lock (LOL) pin is asserted high. In this state, the PLL will
periodically try to reacquire lock with the incoming data
stream. During reacquisition, the recovered clock may
drift over a ±600 ppm range relative to the applied
reference clock, and the LOL output alarm may toggle
until the PLL has reacquired frequency lock. Due to the
low noise and stability of the DSPLL, under the
condition where data is removed from the inputs, there
is the possibility that the PLL will not drift enough to
render an out-of-lock condition.
If REFCLK is removed, the LOL output alarm will always
be asserted when it has been determined that no
activity exists on REFCLK, indicating the frequency lock
status of the PLL is unknown.
Note: LOL is not asserted during PWRDN/CAL.
4.7. PLL Performance
The PLL implementation used in the Si5020 is fully
compliant with the jitter specifications proposed for
SONET/SDH equipment by Bellcore GR-253-CORE,
Issue 2, December 1995 and ITU-T G.958.
4.7.1. Jitter Tolerance
The Si5020’s tolerance to input jitter exceeds that of the
Bellcore/ITU mask shown in Figure 4. This mask
defines the level of peak-to-peak sinusoid jitter that
must be tolerated when applied to the differential data
input of the device.
Note: There are no entries in the mask table for the data rate
corresponding to OC-24 as that rate is not specified by
either GR-253 or G.958.
Figure 4. Jitter Tolerance Specification
4.7.2. Jitter Transfer
The Si5020 is fully compliant with the relevant Bellcore/
ITU specifications related to SONET/SDH jitter transfer.
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter as a function of jitter frequency (see
Figure 5). These measurements are made with an input
test signal that is degraded with sinusoidal jitter whose
magnitude is defined by the mask in Figure 4.
4.7.3. Jitter Generation
The Si5020 exceeds all relevant specifications for jitter
generation proposed for SONET/SDH equipment. The
jitter generation specification defines the amount of jitter
that may be present on the recovered clock and data
outputs when a jitter free input signal is provided. The
Si5020 typically generates less than 3.0 mUIrms of jitter
when presented with jitter-free input data.
f0
f1
f2
f3
ft
Frequency
0.15
1.5
15
Sinusoidal
Input
Jitter (UI p-p)
Slope = 20 dB/Decade
SONET
Data Rate
F0
(Hz)
F1
(Hz)
F2
(Hz)
F3
(kHz)
Ft
(kHz)
OC- 12
OC- 3
10
30
300
25
6.5
250
65
OC- 48
10
600
6000
1000
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5020-B-GMR | 功能描述:計時器和支持產(chǎn)品 Multi-Rate SONET SDH CDR RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| SI5020-BM | 功能描述:計時器和支持產(chǎn)品 SNT/SDH GbE 2.7Gbps OC48/12/3 STM16/4/1 RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| SI5020-BMR | 功能描述:計時器和支持產(chǎn)品 SNT/SDH GbE 2.7Gbps OC48/12/3 STM16/4/1 RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| SI5020C-BA | 功能描述:時鐘和定時器開發(fā)工具 Multi-Rate SONET/ SDH CDR Morph Board RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5020C-BAR | 制造商:Silicon Laboratories Inc 功能描述: |
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