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參數(shù)資料
| 型號： | SI5017-D-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 5/26頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 28MLP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | DSPLL® |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR） |
| PLL： | 是 |
| 主要目的： | SONET/SDH，ATM 應(yīng)用 |
| 輸入： | 時鐘 |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-MLP-EP（5x5） |
| 包裝： | 管件 |
| 其它名稱： | 336-1279 |
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Si5017
13
Rev. 1.5
4.5. Lock Detect
The Si5017 provides lock-detect circuitry that indicates
whether the PLL has achieved frequency lock with the
incoming data. The operation of the lock-detector
depends on the reference clock option used.
When an external reference clock is provided, the circuit
compares the frequency of a divided-down version of
the recovered clock with the frequency of the applied
reference clock (REFCLK). If the recovered clock
frequency deviates from that of the reference clock by
the amount specified in Table 4 on page 9, the PLL is
declared out of lock, and the loss-of-lock (LOL) pin is
asserted. In this state, the PLL will periodically try to
reacquire lock with the incoming data stream. During
reacquisition, the recovered clock frequency (CLKOUT)
drifts over a ±600 ppm range relative to the applied
reference clock and the LOL output alarm may toggle
until the PLL has reacquired frequency lock. Due to the
low noise and stability of the DSPLL, there is the
possibility that the PLL will not drift enough to render an
out-of-lock condition, even if the data is removed from
inputs.
In applications requiring a more stable output clock
during out-of-lock conditions, the lock-to-reference
(LTR) input can be used to force the PLL to lock to the
externally supplied reference.
In the absence of an external reference, the lock detect
circuitry uses a data quality measure to determine when
frequency lock has been lost with the incoming data
stream. During reacquisition, CLKOUT may vary by
approximately ±10% from the nominal data rate.
4.6. Lock-to-Reference
The LTR input is used to force a stable output clock
when an alarm condition, like LOS, exists. In typical
applications, the LOS output is tied to the LTR input to
force a stable output clock when the input data signal is
lost. When LTR is asserted, the DSPLL is prevented
from acquiring the data signal present on DIN. The
operation of the LTR control input depends on which
reference clocking mode is used.
When an external reference clock is present, assertion
of LTR forces the DSPLL to lock CLKOUT to the
provided reference. If no external reference clock is
used, LTR forces the DSPLL to hold the digital
frequency control input to the VCO at the last value.
This produces a stable output clock as long as supply
and temperature are constant.
4.7. Loss-of-Signal (LOS)
The Si5017 indicates a loss-of-signal condition on the
LOS output pin when the input peak-to-peak signal level
on DIN falls below an externally controlled threshold.
The LOS threshold range is specified in Table 3 and is
set by applying a voltage on the LOS_LVL pin. The
graph in Figure 6 illustrates the LOS_LVL mapping to
the LOS threshold. The LOS output is asserted when
the input signal drops below the programmed peak-to-
peak value. If desired, the LOS function may be
disabled by grounding LOS_LVL or by adjusting
LOS_LVL to be less than 1 V.
Note: The LOS circuit is designed to only work with pseudo-
random, dc-balanced data.
Figure 6. LOS_LVL Mapping
Figure 7. LOS Signal Hysteresis
Table 7. Typical REFCLK Frequencies
SONET/SDH
OC-48 with
15/14 FEC
Ratio of VCO
to REFCLK
19.44 MHz
20.83 MHz
128
77.76 MHz
83.31 MHz
32
155.52 MHz 166.63 MHz
16
40mV/V
0 mV
0 V
LOS_LVL (V)
LOS
Th
res
h
old
(m
V
PP
)
30 mV
2.25 V
1.50 V
1.00 V
15 mV
LOS
D
isable
d
LO
S
Un
de
fi
ne
d
1.875 V
40 mV
2.50 V
LOS Limited by Device Noise
9
3
LOS
LOS_LVL
R1
R2
10k
Si5017
CDR
LOS Alarm
Set LOS
Level
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5017-D-GMR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 OC48/STM16 CDR FEC RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5017-EVB | 功能描述:時鐘和定時器開發(fā)工具 OC48 STM16 SNT/SDH 2.7Gbps w/ limit amp RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5017-X-GM | 制造商:SILABS 制造商全稱:SILABS 功能描述:OC-48/STM-16 SONET/SDH CDR IC WITH LIMITING AMPLIFIER |
| SI5018 | 制造商:SILABS 制造商全稱:SILABS 功能描述:SiPHY⑩ OC-48/STM-16 CLOCK AND DATA RECOVERY IC WITH FEC |
| SI-50182 | 制造商:BEL 制造商全稱:Bel Fuse Inc. 功能描述:SI-50182 |
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