參數(shù)資料
型號(hào)： SI4122-D-GTR
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 10/36頁(yè)
文件大?。?/td> 0K
描述： IC SYNTHESIZER RF2/IF 24TSSOP
標(biāo)準(zhǔn)包裝： 2,500
類(lèi)型： 頻率合成器
PLL： 是
輸入： 時(shí)鐘
輸出： 時(shí)鐘
電路數(shù)： 1
比率 - 輸入:輸出： 1:2
差分 - 輸入:輸出： 無(wú)/無(wú)
頻率 - 最大： 1.5GHz
除法器/乘法器： 是/無(wú)
電源電壓： 2.7 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 帶卷 (TR)
Si4133
18
Rev. 1.61
for how to select LDETB. The LDETB
signal is low after self-tuning is completed but rises
when the IF or RF PLL nears the limit of its
compensation range. LDETB is also high when either
PLL is executing the self-tuning algorithm. The output
frequency is still locked when LDETB goes high, but the
PLL eventually loses lock if the temperature continues
to drift in the same direction. Therefore, if LDETB goes
high both the IF and RF PLLs should be re-tuned
promptly by initiating the self-tuning algorithm.
3.5. Output Frequencies
The IF and RF output frequencies are set by
programming the R- and N-Divider registers. Each PLL
has R and N registers so that each can be programmed
independently. Programming either the R- or N-Divider
register for RF1 or RF2 automatically selects the
associated output.
The reference frequency on the XIN pin is divided by R
and this signal is input to the PLL’s phase detector. The
other input to the phase detector is the PLL’s VCO
output frequency divided by N. The PLL acts to make
these frequencies equal.
That is, after an initial transient:
or
The R values are set by programming the RF1 R-
Divider register (Register 6), the RF2 R-Divider register
(Register 7) and the IF R-Divider register (Register 8).
The N values are set by programming the RF1 N-
Divider register (Register 3), the RF2 N-Divider register
(Register 4), and the IF N-Divider register (Register 5).
Each N-Divider is implemented as a conventional high
speed divider. That is, it consists of a dual-modulus
prescaler, a swallow counter, and a lower speed
synchronous counter. However, the control of these
sub-circuits
is
automatically
handled.
Only
the
appropriate N value should be programmed.
3.6. PLL Loop Dynamics
The transient response for each PLL is determined by
its phase detector update rate f (equal to fREF/R) and
the phase detector gain programmed for each RF1,
RF2, or IF synthesizer. See Register 1. Four different
settings for the phase detector gain are available for
each PLL. The highest gain is programmed by setting
the two phase detector gain bits to 00, and the lowest by
setting the bits to 11. The values of the available gains,
relative to the highest gain, are as follows:
The gain value bits is automatically set with the Auto KP
bit (bit 2) in the Main Configuration register to 1. In
setting this bit, the gain values are optimized for a given
value of N. In general, a higher phase detector gain
decreases in-band phase noise and increase the speed
of the PLL transient until the point at which stability
begins to be compromised. The optimal gain depends
on N. Table 9 lists recommended settings for different
values of N. These are the settings when the Auto KP bit
is set.
The VCO gain and loop filter characteristics are not
programmable.
The settling time for the PLL is directly proportional to its
phase detector update period T (T equals 1/f). A
typical transient response is shown in Figure 6 on page
11. During the first 13 update periods the Si4133
executes the self-tuning algorithm. From then on the
PLL controls the output frequency. Because of the
unique architecture of the Si4133 PLLs, the time
required to settle the output frequency to 0.1 ppm error
is automatically 25 update periods. The total time after
powerup or a change in programmed frequency until the
synthesized frequency is settled—including time for
self-tuning—is approximately 40 update periods.
Note: The settling time analysis holds for RF1 f
500 kHz.
For RF1 f
> 500 kHz, the settling time is larger.
f
OUT
N
------------
f
REF
R
-----------
=
f
OUT
N
R
----
f
REF
=
Table 8. Gain Values (Register 1)
KP Bits
Relative P.D.
Gain
00
1
01
1/2
10
1/4
11
1/8
Table 9. Optimal KP Settings
N
RF1
KP1<1:0>
RF2
KP2<3:2>
IF
KPI<5:4>
2047
00
2048 to 4095
00
01
4096 to 8191
00
01
10
8192 to 16383
01
10
11
16384 to 32767
10
11
32768
11
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