參數(shù)資料
型號(hào): SI3230-E-FM
廠商: Silicon Laboratories Inc
文件頁數(shù): 106/108頁
文件大小: 0K
描述: IC SLIC PROG 1-CH 38QFN
標(biāo)準(zhǔn)包裝: 364
系列: ProSLIC®
功能: 用戶線路接口概念(SLIC)
接口: SPI
電路數(shù): 1
電源電壓: 3.13 V ~ 5.25 V
電流 - 電源: 88mA
功率(瓦特): 700mW
安裝類型: 表面貼裝
封裝/外殼: 38-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 38-QFN(5x7)
包裝: 托盤
包括: DTMF 生成和解碼,F(xiàn)SK 生成
Si3230
Preliminary Rev. 0.96
97
Not
Recommended
fo
r N
ew
D
esi
gn
s
4.5. FSK Control
For detailed instructions on FSK signal generation, refer to “Application Note 32: FSK Generation” (AN32). These
registers support enhanced FSK generation mode, which is enabled by setting FSKEN = 1 (direct Register 108,
bit 6) and REL = 1 (direct Register 32, bit 6).
31
Common Mode Maximum Threshold for Speed-Up.
This register defines the positive common mode voltage threshold. Exceeding this
threshold enables a wider bandwidth of dc linefeed control for faster settling times. The
range is 0–23.625 V in 0.375 V steps.
32
Power Alarm Threshold for Transistors Q1 and Q2.
33
Power Alarm Threshold for Transistors Q3 and Q4.
34
Power Alarm Threshold for Transistors Q5 and Q6.
35
Loop Closure Filter Coefficient.
36
Ring Trip Filter Coefficient.
37
Thermal Low Pass Filter Pole for Transistors Q1 and Q2.
38
Thermal Low Pass Filter Pole for Transistors Q3 and Q4.
39
Thermal Low Pass Filter Pole for Transistors Q5 and Q6.
40
Common Mode Bias Adjust During Ringing.
Recommended value of 0 decimal.
41
DC-DC Converter VOV Voltage (Si3230 only).
This register sets the overhead voltage, VOV, to be supplied by the dc-dc converter.
When the VOV bit = 0 (direct Register 66, bit 4), VOV should be set between 0 and 9 V
(VMIND = 0 to 6h). When the VOV bit = 1, VOV should be set between 0 and 13.5 V
(VMIND = 0 to 9h).
42
Reserved.
43
Loop Closure Threshold—Lower Bound.
This register defines the lower threshold for loop closure hysteresis, which is enabled in
bit 0 of direct Register 108. The range is 0–80 mA in 1.27 mA steps.
Table 39. FSK Control Indirect Registers Summary
Addr. D15
D14
D13
D12
D11
D10
D9
D8D7D6D5D4D3D2D1
D0
99
FSK0X[15:0]
100
FSK0[15:0]
101
FSK1X[15:0]
102
FSK1[15:0]
103
FSK01[15:0]
104
FSK10[15:0]
Table 38. SLIC Control Indirect Registers Description (Continued)
Addr.
Description
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