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    參數(shù)資料
    型號: SI3220-G-FQ
    廠商: Silicon Laboratories Inc
    文件頁數(shù): 106/112頁
    文件大?。?/td> 0K
    描述: IC PROSLIC/CODEC DUAL 64TQFP
    標(biāo)準(zhǔn)包裝: 160
    系列: ProSLIC®
    功能: 用戶線路接口概念(SLIC),CODEC
    接口: GCI,PCM,SPI
    電路數(shù): 2
    電源電壓: 3.3V,5V
    電流 - 電源: 65mA
    功率(瓦特): 941mW
    工作溫度: 0°C ~ 70°C
    安裝類型: 表面貼裝
    封裝/外殼: 64-TQFP
    供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
    包裝: 托盤
    包括: 電池切換,BORSCHT 功能,DTMF 生成和解碼,F(xiàn)SK 音調(diào)生成,調(diào)制解調(diào)器和傳真音調(diào)檢測
    Si3220/25 Si3200/02
    Rev. 1.3
    93
    Not
    Recommended
    fo
    r N
    ew
    D
    esi
    gn
    s
    monitor channel section. This section defines the
    functionality of the six C/I bits whether they are being
    transmitted to the GCI bus via the DTX pin (upstream)
    or received from the GCI bus via the DRX pin
    (downstream). The structure of the SC channel is
    shown in Figure 62.
    Figure 62. SC Channel Structure
    3.31.9. Downstream (Receive) SC Channel Byte
    The first six bits in the downstream SC channel control
    both channels of the Dual ProSLIC where the C/I bits
    are defined as follows:
    Figure 63 illustrates the transmission protocol for the C/I
    bits within the downstream SC channel. New data
    received by either channel must be present and match
    for two consecutive frames to be considered valid.
    When a new command is communicated via the
    downstream C/I bits, this data must be sent for at least
    two consecutive frames to be recognized by the Dual
    ProSLIC.
    The current state of the C/I bits is stored in a primary
    register, P. If the received C/I bits are identical to the
    current state, no action is taken. If the received C/I bits
    differ from those in register P, the new set of C/I bits is
    loaded into secondary register S, and a latch is set.
    When the next set of C/I bits is received during the
    frame that immediately follows, the following rules
    apply:
    If the received C/I bits are identical to the contents of
    register S, the stored C/I bits are loaded into register
    P, and a valid C/I bit transition is recognized. The
    latch is reset, and the Dual ProSLIC responds
    accordingly to the command represented by the new
    C/I bits.
    If the received C/I bits differ from both the contents of
    register S and the contents of register P, the newly-
    received C/I bits are loaded into register S, and the
    latch remains set. This cycle continues as long as
    any new set of C/I bits differs from the contents of
    registers S and P.
    If the newly-received C/I bits are identical to the
    contents of register P, the contents of register P
    remain unchanged, and the latch is reset.
    MSB
    LSB
    76
    543
    2
    1
    0
    CI2A
    CI1A
    CI0A
    CI2B
    CI1B
    CI0B
    MR
    MX
    CI2A, CI1A, CI0A
    Used to select operating mode for
    channel A
    CI2B, CI1B, CI0B
    Used to select operating mode for
    channel B
    MR, MX
    Monitor channel handshake bits
    Table 49. Programming Operating Modes Using
    Downstream SC Channel C/I Bits
    Channel Specific C/I bits
    Dual ProSLIC Operating
    Mode
    CI2x
    CI1x
    CI0x
    0
    Open (high impedence,
    no line monitoring)
    0
    1
    Forward Active
    0
    1
    0
    Forward On-Hook Trans-
    mission
    0
    1
    Ground Start (Tip Open)
    100
    Ringing
    1
    0
    1
    Reverse Active
    1
    0
    Reverse On-Hook Trans-
    mission
    1
    Ground Start (Ring
    Open)
    Note:
    x = A or B, corresponding to Channel A or
    Channel B.
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