參數(shù)資料
型號： SI3216-FT
廠商： Silicon Laboratories Inc
文件頁數(shù)： 58/122頁
文件大?。?/td> 0K
描述： IC SLIC/CODEC 1CH 38TSSOP
標準包裝： 50
系列： ProSLIC®
功能： 用戶線路接口概念（SLIC），CODEC
接口： GCI，PCM，SPI
電路數(shù)： 1
電源電壓： 3.13 V ~ 5.25 V
電流 - 電源： 88mA
功率（瓦特）： 700mW
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 38-TFSOP（0.173"，4.40mm 寬）
供應商設備封裝： 38-TSSOP
包裝： 管件
包括： 音頻音調(diào)生成，BORSCHT 功能，F(xiàn)SK 生成，振鈴和電池電壓生成
Si3216
40
Rev. 1.0
Not
Recommended
fo
r N
ew
D
esi
gn
2.4.2. Sinusoidal Ringing
To configure the ProSLIC for sinusoidal ringing, the
frequency and amplitude are initialized by writing to the
following indirect registers: RCO, RNGX, and RNGY.
The equations for RCO, RNGX, RNGY are as follows:
where
and f = desired ringing frequency in hertz.
In selecting a ringing amplitude, the peak TIP-to-RING
ringing voltage must be greater than the selected on-
hook line voltage setting (VOC, direct Register 72). For
example, to generate a 70 VPK 20 Hz ringing signal, the
equations are as follows:
In addition, the user must select the sinusoidal ringing
waveform by writing TSWS = 0 (direct Register 34,
bit 0).
2.4.3. Trapezoidal Ringing
In addition to the sinusoidal ringing waveform, the
ProSLIC
supports
trapezoidal
ringing.
illustrates a trapezoidal ringing waveform with offset
VROFF.
Table 29. Registers for Ringing Generation
Parameter
Range/ Description
Register
Bits
Location
Ringing Waveform
Sine/Trapezoid
TSWS
Ringing Voltage Offset Enable
Enabled/
Disabled
RVO
Ringing Active Timer Enable
Enabled/
Disabled
RTAE
Ringing Inactive Timer Enable
Enabled/
Disabled
RTIE
Ringing Oscillator Enable
Enabled/
Disabled
ROE
Ringing Oscillator Active Timer
0 to 8 s
RAT[15:0]
Direct Registers 48 and
Ringing Oscillator Inactive Timer
0 to 8 s
RIT[15:0]
Direct Registers 50 and
Linefeed Control (Initiates Ringing State)
Ringing State = 100b
LF[2:0]
High Battery Voltage
0 to –94.5 V
VBATH[5:0]
Ringing dc voltage offset
0 to 94.5 V
ROFF[15:0]
Indirect Register 6
Ringing frequency
15 to 100 Hz
RCO[15:0]
Indirect Register 7
Ringing amplitude
0 to 94.5 V
RNGX[15:0]
Indirect Register 8
Ringing initial phase
Sets initial phase for
sinewave and period
for trapezoid
RNGY[15:0]
Indirect Register 9
Common Mode Bias Adjust During Ringing
0 to 22.5 V
VCMR[3:0]
Indirect Register 27
Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped
directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through
31).
RCO
coeff
2
15
=
coeff
2
f
1000 Hz
-----------------------
cos
=
RNGX
1
4
---
1
coeff
–
1coeff
+
------------------------
2
15
Desired V
PK 0to 94.5 V
96 V
------------------------------------------------------------------------
=
RNGY
0
=
coeff
2
20
1000 Hz
-----------------------
0.99211
=
cos
=
RCO
0.99211
2
15
32509
7EFDh
==
=
RNGX
1
4
---
0.00789
1.99211
---------------------
2
15
70
96
------
376
0177h
=
=
RNGY
0
=
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