參數(shù)資料
型號： SI3201-KS
廠商： Silicon Laboratories Inc
文件頁數(shù)： 101/148頁
文件大?。?/td> 0K
描述： IC LINEFEED INTRFC SI321X 16SOIC
標準包裝： 48
系列： ProSLIC®
功能： CODEC
接口： PCM，串行，SPI
電路數(shù)： 1
電源電壓： 3.13 V ~ 5.25 V
電流 - 電源： 88mA
功率（瓦特）： 800mW
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm Width）裸露焊盤
供應(yīng)商設(shè)備封裝： 16-SOIC N
包裝： 管件
包括： BORSCHT 功能，振鈴往返檢測
Si3210/Si3211
56
Rev. 1.61
Not
Recommended
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r N
ew
D
esi
gn
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2.12. PCM Interface
The ProSLIC contains a flexible programmable interface for the transmission and reception of digital PCM
samples. PCM data transfer is controlled via the PCLK and FSYNC inputs as well as PCM Mode Select (direct
Register 1), PCM Transmit Start Count (direct registers 2 and 3), and PCM Receive Start Count (direct registers 4
and 5). The interface can be configured to support from 4 to 128 8-bit timeslots in each frame. This corresponds to
PCLK frequencies of 256 kHz to 8.192 MHz in power of 2 increments. (768 kHz and 1.536 MHz are also available,
but these frequencies are not valid for GCI mode.) Timeslots for data transmission and reception are independently
configured using the TXS and RXS registers. By setting the correct starting point of the data, the ProSLIC can be
configured to support long FSYNC and short FSYNC variants as well as IDL2 8-bit, 10-bit, B1 and B2 channel time
slots. DTX data is high-impedance except for the duration of the 8-bit PCM transmit.
DTX will return to high impedance either on the negative edge of PCLK during the LSB or on the positive edge of
PCLK following the LSB. This is based on the setting of the TRI bit of the PCM Mode Select register. Tristating on
the negative edge allows the transmission of data by multiple sources in adjacent timeslots without the risk of driver
contention. In addition to 8-bit data modes, there is a 16-bit mode provided. This mode can be activated via the
PCMT bit of the PCM Mode Select register. GCI timing is also supported in which the duration of a data bit is two
PCLK cycles. This mode is also activated via the PCM Mode Select register. Setting the TXS or RXS register
greater than the number of PCLK cycles in a sample period will stop data transmission because TXS or RXS will
never equal the PCLK count. Figures 29–32 illustrate the usage of the PCM highway interface to adapt to common
PCM standards.
Figure 29. Example, Timeslot 1, Short FSYNC (TXS/RXS = 1)
Figure 30. Example, Timeslot 1, Long FSYNC (TXS/RXS = 0)
01
7
6
5
4
3
2
16
15
14
13
12
11
10
9
818
17
MSB
LSB
MSB
LSB
HI-Z
PCLK
FSYNC
PCLK_CNT
DRX
DTX
01
7
6
5
4
3
2
16
15
14
13
12
11
10
9
818
17
MSB
LSB
MSB
LSB
HI-Z
PCLK
FSYNC
PCLK_CNT
DRX
DTX
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