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參數(shù)資料
| 型號(hào)： | SI3050-E1-GT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 62/128頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC VOICE DAA SYSTEM SIDE 24QFN |
| 標(biāo)準(zhǔn)包裝： | 74 |
| 系列： | * |
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Si3050 + Si3011/18/19
Rev. 1.5
39
5.29. Filter Selection
The Si3050 supports additional filter selections for the
receive and transmit signals as defined in Tables 10 and
11. The IIRE bit (Register 16, bit 4) selects between the
IIR and FIR filters. The IIR filter provides a shorter, but
non-linear, group delay alternative to the default FIR
filter, and only operates with an 8 kHz sample rate. The
FILT
bit
(Register 31, bit 1)
selects
a
–3 dB
low
frequency pole of 5 Hz when cleared and a –3 dB low
frequency pole of 200 Hz (per EIA/TIA 464) when set.
The FILT bit affects the receive path only.
5.30. Clock Generation
The Si3050 generates the necessary internal clock
frequencies from the PCLK input. PCLK must be
synchronous to the 8 kHz FSYNC clock and run at one
of the following rates: 256kHz, 512kHz, 768kHz,
1.024 MHz,
1.53 MHz,
2.048 MHz,
4.09 MHz,
or
8.192 MHz. The ratio of the PCLK rate to the FSYNC
rate is determined internally by the DAA and is
transferred into internal registers after a reset. These
internal registers are not accessible through register
reads or writes. Figure 29 shows the operation of the
Si3050 clock circuitry.
The PLL clock synthesizer settles quickly after powerup.
However, the settling time depends on the PCLK
frequency and it can be approximately predicted by the
following equation:
Tsettle =64/FPCLK
For all valid PCLK frequencies listed above, the default
line sample rate is 8 kHz. This sample rate can be
increased
to
16 kHz
by
setting
the
HSSM
bit
(Register 7, bit 3). Regardless of the sample rate
frequency, the serial data communication rate of the
PCM and GCI highways remains 8 kHz. When the
16 kHz sample rate is selected, additional timeslots in
the PCM or GCI highway are used to transfer the
additional data.
5.31. Communication Interface Mode
Selection
The Si3050 supports two communication interface
protocols:
PCM/SPI mode where data and control information
transmission/reception occurs across separate
buses (PCM highway for data, and SPI port for
control).
GCI mode where data and control information is
multiplexed and transmission/reception occurs
across the GCI highway bus.
A pin-strapping method (specifically, the state of SCLK
on power-up [reset]) is used to select between the two
specify how to select a communication mode, and how
the various pins are used in each mode.
When operating in PCM/SPI mode, the GCI control
register should not be written (i.e., Register 42 must
each remain set at 0000_0000 when using the PCM/
SPI highway mode). Similarly, when operating in GCI
highway mode the PCM registers should not be written
(i.e., Registers 33–37 must remain set to 0000_0000
when using the GCI highway mode).
Figure 29. PLL Clock Synthesizer
PFD
VCO
2
16.384 MHz
DIV M
PCLK
Internal PLL
Register
2
N
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| SI3050-E1-GTR | 制造商:Silicon Laboratories Inc 功能描述:SI3050 VOICE DAA SYSTEM-SIDE - Tape and Reel 制造商:Silicon Laboratories Inc 功能描述:IC VOICE DAA SYSTEM SIDE 24QFN 制造商:Silicon Laboratories Inc 功能描述:Si3050 Voice DAA System-Side |
| Si3050-E-FM | 功能描述:電信語(yǔ)音調(diào)制 IC Si3050 Voice DAA System-Side RoHS:否 制造商:Epson Electronics America 產(chǎn)品: 應(yīng)用:Voice Guidance product 封裝 / 箱體:PQFP-52 電源電壓-最大:3.6 V, 5.5 V 最大工作溫度: 最小工作溫度: 封裝: |
| SI3050-E-FMR | 功能描述:電信線路管理 IC Si3050 Voice DAA System-Side RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| SI3050-E-FS | 制造商:SILABS 制造商全稱:SILABS 功能描述:GLOBAL VOICE DAA |
| SI3050-E-FSR | 制造商:SILABS 制造商全稱:SILABS 功能描述:PCM highway data interface law A-law companding SPI control interface GCl interface |
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