參數(shù)資料
型號: SI3050-E1-FT
廠商: Silicon Laboratories Inc
文件頁數(shù): 18/128頁
文件大小: 0K
描述: IC VOICE DAA SYSTEM SIDE 20TSSOP
標(biāo)準(zhǔn)包裝: 74
系列: *
Si3050 + Si3011/18/19
114
Rev. 1.5
Table 31. 24-Pin Quad Flat No-Lead (QFN) PCB Land Pattern Dimensions
Symbol
MIN
NOM
MAX
P1
2.10
2.20
2.30
P2
2.10
2.20
2.30
X1
0.20
0.25
0.30
Y1
0.75
0.80
0.85
C1
3.90
C2
3.90
E0.50
Notes:
General
1.
All dimensions shown are in millimeters (mm) unless otherwise noted.
2.
Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3.
This Land Pattern Design is based on the IPC-7351 guidelines.
Solder mask design
1.
All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 mm minimum, all the
way around the pad.
Stencil Design
1.
A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls
should be used to assure good solder paste release.
2.
The stencil thickness should be 0.125mm (5 mils).
3.
The ratio of stencil aperture to land pad size should be 1:1 for all perimeter
pins.
4.
A 2 x 2 array of 0.90 mm square openings on 1.20 mm pitch should be used
for the center ground pad.
Card Assembly
1.
A No-Clean, Type-3 solder paste is recommended.
2.
The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
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