參數(shù)資料
型號: SHM-4860MM
廠商: Electronic Theatre Controls, Inc.
元件分類: 運動控制電子
英文描述: Industry-Standard, High-Speed 【0.01% Sample-Hold Amplifiers
中文描述: 工業(yè)標準,高速【0.01%采樣保持放大器
文件頁數(shù): 2/3頁
文件大?。?/td> 54K
代理商: SHM-4860MM
Sample-and-Hold Amplifiers
SHM-4860
PHYSICAL/ENVIRONMENTAL
Operating Temperature Ranges
SHM-4860MC
SHM-4860MM, 883
Storage Temperature Range
Package Type
0 to +70°C (ambient)
–55 to +125°C (case)
–65 to +150°C
24-pin ceramic DDIP
Footnotes:
Input signal should not exceed the supply voltage.
The SHM-4860’s output is current limited at approximately ±65mA. The device
can withstand a sustained short to ground. However, shorts from the output to
either supply will cause permanent damage. For normal operation, the load
current should not exceed ±40mA.
Full Scale (FS) = 10V. Full Scale Range (FSR) = 20V.
Sample-to-Hold Offset Error (Pedestal) is constant regardless of input/output
level.
Units are ppm of FSR/°C.
ABSOLUTE MAXIMUM RATINGS
±15V Supply Voltages, Pins 24, 22
+5V Supply Voltage, Pin 9
Analog Input, Pin 13
Digital Inputs, Pins 11, 12
Output Current
±18V
–0.5V to +7V
±18V
–0.5V to +7V
±65mA
FUNCTIONAL SPECIFICATIONS
(Typical at +25°C with ±15V and +5V supplies unless otherwise noted.)
ANALOG INPUT/OUTPUT
MIN.
TYP.
MAX.
UNITS
Input/Output Voltage Range
Input Impedance
Output Current
Output Impedance
Maximum Capacitive Load
±10.25
±11.25
1
0.1
250
±40
V
k
mA
k
pF
DIGITAL INPUT
Input Logic Level
Logic "1"
Logic "0"
Loading
Logic "1"
Logic "0"
+2.0
0
+5.0
+0.8
V
V
+40
–1.6
μA
mA
TRANSFER CHARACTERISTICS
Gain
Gain Accuracy
Gain Linearity Error
Sample-Mode Offset Voltage
Sample-to-Hold Offset Error
(Pedestal)
Gain Tempco
(Drift)
Sample-Mode Offset Drift
Sample-to-Hold Offset Drift
–1
±0.1
±0.01
±5
V/V
%
%FS
mV
±0.05
±0.005
±0.5
±2.5
±0.5
±3
±4
±20
±5
±15
mV
ppm/°C
DYNAMIC CHARACTERISTICS
Acquisition Time
10V to ±0.01%FS
10V to ±0.1%FS
10V to ±1%FS
1V to ±1%FS
Sample-to-Hold Settling Time
10V to ±0.01%FS
10V to ±0.1%FS
Sample-to-Hold Transient
Aperture Delay Time
Aperture Uncertainty
(Jitter)
Output Slew Rate
Small Signal Bandwidth
(–3dB)
Droop:
+25°C
+70°C
+125°C
Feedthrough Attenuation
Overload Recovery Time
Positive
Negative
160
100
90
75
200
170
ns
ns
ns
ns
60
40
180
6
±50
±300
16
±0.5
±15
±1.2
74
100
±5
ns
ns
mV p-p
ns
ps
μ
V/
μ
s
MHz
μ
V/
μ
s
μ
V/
μ
s
mV/
μ
s
dB
200
700
ns
ns
POWER REQUIREMENTS
Voltage Range:
±15V Supplies
±3
±5
±0.5
%
%
+5V Supply
Power Supply Rejection Ratio
Quiescent Current Drain
+15V Supply
–15V Supply
+5V Supply
Power Consumption
mV/V
+21
–22
+17
730
+25
–25
+25
875
mA
mA
mA
mW
TECHNICAL NOTES
1. All ground pins (10, 15, 21, 23) should be tied together and
connected to system analog ground as close to the package
as possible. It is recommended to use a ground plane
under the device and solder all four ground pins directly to
it. Care must be taken to ensure that no ground potentials
can exist between Pin 10 and the other ground pins.
2. Although the power supply pins (9, 22, 24) are internally
bypassed to ground with 0.01μF ceramic capacitors,
additional external 0.1μF to 1μF tantalum bypass
capacitors may be required in critical applications.
3. A logic "0" on the HOLD COMMAND input (Pin 11), or a
logic "1" on the HOLD COMMAND input (Pin 12), will put
the device in the sample mode. In this mode, the device
acts as an inverting unity-gain amplifier, and its output will
track its input. A logic "1" on Pin 11 (logic "0" on Pin 12)
will put the device in the hold mode, and the output will be
held constant at the last input level present when the hold
command was given.
If the HOLD COMMAND input (Pin 11) is used to control the
device, Pin 12 must be tied to digital ground. If HOLD
COMMAND input (Pin 12) is used to control the device, Pin
11 must be tied to +5V.
4. The maximum capacitive load to avoid oscillation is typically
250pF. Recommended resistive load is 500
, although
values as low as 250
may be used. Acquisition and
sample-to-hold settling times are relatively unaffected by
resistive loads down to 250
and capacitive loads up to
50pF. However, higher capacitances will affect both
acquisition and settling time.
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