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參數(shù)資料
| 型號： | SG6980DZ |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Single-Stage PFC Controller |
| 中文描述： | POWER FACTOR CONTROLLER, 68 kHz SWITCHING FREQ-MAX, PDIP16 |
| 封裝： | LEAD FREE, PLASTIC, DIP-16 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 734K |
| 代理商： | SG6980DZ |
Product Specification
Single-Stage PFC Controller
Protections & Built-in Latch Circuit
SG6980
System General Corp.
Version 1.0.1 (IAO33.0064.B0)
- 14 -
www.sg.com.tw www.fairchildsemi.com
September 17, 2007
The SG6980 provides full protection functions to prevent
the power supply and the load from being damaged. The
protection features include:
PFC Feedback Over-Voltage Protection.
When the PFC
feedback voltage exceeds the over-voltage threshold, the
SG6980 inhibits the PFC switching signal. This
protection prevents the PFC power converter from
operating abnormally while the FB pin is open.
PFC Feedback Under-Voltage Protection.
The SG6980
stops the PFC switching signal whenever the PFC
feedback voltage drops below the under-voltage threshold.
This protection feature is designed to prevent the PFC
power converter from experiencing abnormal conditions
while the FB pin is shorted to ground.
VDD Over-Voltage Protection.
The built-in clamping
circuit clamps V
DD
whenever the V
DD
voltage exceeds the
over-voltage threshold.
RI Pin Open / Short Protection.
The RI pin is used to set
the switching frequency and internal current reference. If
the RI pin is short or open, SG6980 is off.
PCB Layout
SG6980 has a single ground pin. High sink currents in the
output therefore cannot be returned separately. Good
high-frequency or RF layout practices should be followed.
Avoid long PCB traces and component leads. Locate
decoupling capacitors near the SG6980. A resistor of 5 ~
20
Ω
is recommended, connecting in series from the
output to the gate of the MOSFET.
Isolating the interference between the PFC and PWM
stages is also important. Figure 7 shows an example of the
PCB layout. The
ground
trace 1
is connected from the
ground pin to the decoupling capacitor, which should be
low impedance and as short as possible. The
ground trace
2
provides a signal ground. It should be connected directly
to the decoupling capacitor C
DD
and/or to the ground pin.
The
ground trace 3
is independently tied from the
decoupling capacitor to the PFC output capacitor C
O
. The
ground in the output capacitor C
O
is the major ground
reference for power switching. To provide a good ground
reference and reduce the switching noise of both the PFC
and PWM stages, the
ground traces 6 and 7
should be
located very near and be low impedance.
The ICS pin is connected directly to R
S
through R
3
to
improve noise immunity. (Beware that it may incorrectly
be connected to the ground trace 2). The IMP and IPK
pins should also be connected directly, via the resistors R
2
and R
P
, to another terminal of R
S
.
FIG. 7 PCB Layout
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