
Product Specification
Low Cost Green-Mode PWM Controller for Flyback Converters
SG6859
System General Corp.
Version 1.2.1(IAO33.0067.B2)
- 8 -
www.sg.com.tw
www.fairchildsemi.com
September 28, 2007
OPERATION DESCRIPTION
SG6859 devices integrate many useful designs into
one controller for low-power switch-mode power supplies.
The following descriptions highlight some of the features
of the SG6859 series.
Start-up Current
The start-up current is only 9uA. Low start-up
current allows a start-up resistor with a high resistance
and a low-wattage to supply the start-up power for the
controller. A 1.5 M
, 0.25W, start-up resistor and a
10uF/25V V
DD
hold-up capacitor would be sufficient for
an AC-to-DC power adapter with a wide input range
(100V
AC
to 240V
AC
).
Operating Current
The operating current has been reduced to 3mA. The
low operating current results in higher efficiency and
reduces the V
DD
hold-up capacitance requirement.
Green-Mode Operation
The proprietary green-mode function provides
off-time modulation to linearly decrease the switching
frequency under light-load conditions. On-time is limited
to provide stronger protection against brownouts and
other abnormal conditions. The feedback current, which is
sampled from the voltage feedback loop, is taken as the
reference. Once the feedback current exceeds the
threshold current, the switching frequency starts to
decrease. This green-mode function dramatically reduces
power consumption under light-load and zero-load
conditions. Power supplies using the SG6859 can easily
meet even the strictest regulations regarding standby
power consumption.
Oscillator Operation
A resistor connected from the RI pin to ground will
generate a constant current source for the SG6859. This
current is used to charge an internal capacitor. The
charge-time determines the internal clock speed and the
switching frequency. Increasing the resistance will reduce
the amplitude of the input current and reduce the
switching frequency. A 95k
resistor R
i
results in a 50uA
constant current I
i
and a 70kHz switching frequency. The
relationship between R
i
and the switching frequency is:
)
(
kHz
)
(k
R
6650
PWM
f
Ω
=
Leading-Edge Blanking
Each time the power MOSFET is switched on, a
turn-on spike will inevitably occur at the sense-resistor.
To avoid premature termination of the switching pulse, a
320nsec leading edge blanking time is built in.
Conventional RC filtering can therefore be omitted.
During this blanking period, the current-limit comparator
is disabled and it cannot switch off the gate driver.
Constant Output Power Limit
When the SENSE voltage across the sense resistor R
s
reaches the threshold voltage (around 0.96V), the output
GATE drive will be turned off following a short
propagation delay t
PD
.
This propagation delay will introduce an additional
current proportional to t
PD
*V
in
/L
p
. The propagation delay
is nearly constant regardless of the input line voltage V
IN
.
Higher input line voltages will result in larger additional
currents. At high input line voltages, the output power
limit will be higher than at low input line voltages.
To compensate for this output power limit variation
across a wide AC input range, the threshold voltage is
adjusted by adding a positive ramp.
This ramp signal rises from 0.80V to 0.96V, and then
flattens out at 0.96V. A smaller threshold voltage forces
the output GATE drive to terminate earlier.
This reduces the total PWM turn-on time and makes
the output power equal to that of low line input. This
proprietary internal compensation ensures a constant
output power limit for a wide AC input voltage range
(90VAC to 264VAC).
Under Voltage Lockout (UVLO)
The turn-on and turn-off thresholds of the SG6859
are fixed internally at 16.5V/11.5V. During start-up, the
hold-up capacitor must be charged to 16.5V through the
start-up resistor, so that the SG6859 will be enabled. The
hold-up capacitor will continue to supply V
DD
until power
can be delivered from the auxiliary winding of the main
transformer. V
DD
must not drop below
11.5V during this
start-up process. This UVLO hysteresis window ensures
that hold-up capacitor will be adequate to supply V
DD
during start-up.