
Product Specification
Highly Integrated Green-Mode PWM Controller
MARKING DIAGRAMS PIN CONFIGURATION
SG5842A/JA
System General Corp.
Version 1.4.2 (IAO33.0026.B6)
- 2 -
www.sg.com.tw www.fairchildsemi.com
October 30, 2007
ORDERING INFORMATION
Part Number
OTP Latch OVP Latch Frequency Hopping Pb-Free
Package
SG5842JASZ
Yes
Yes
Yes
8-Pin SOP
SG5842JADZ
Yes
Yes
Yes
8-Pin DIP
SG5842ASZ (Preliminary)
Yes
Yes
No
8-Pin SOP
SG5842ADZ (Preliminary
Yes
Yes
No
8-Pin DIP
PIN DESCRIPTIONS
Pin No. Symbol
Function
Description
1
GND
Ground
Ground.
2
FB
Feedback
The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is
determined in response to the signal from this pin and the current-sense signal from Pin 6. If FB
voltage exceeds the threshold, the internal protection circuit disables PWM output after a
predetermined delay time.
3
VIN
Start-up Input
For start-up, this pin is pulled high to the rectified line input via a resistor. Since the start-up
current requirement of the SG5842A/JA is very small, a large start-up resistance can be used
to minimize power loss.
4
RI
Reference
Setting
A resistor connected from the RI pin to GND pin provides a constant current source. This
determines the center PWM frequency. Increasing the resistance reduces PWM frequency.
Using a 26K
resistor results in a 65KHz center PWM frequency.
5
RT
Temperature
Detection
For over-temperature protection. An external NTC thermistor is connected from this pin to the
GND pin. The impedance of the NTC decreases at high temperatures. Once the voltage of the
RT pin drops below a fixed limit, PWM output is latched off.
6
SENSE
Current Sense
Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle
current limiting.
7
VDD
Power Supply
Power supply. The internal protection circuit disables PWM output if V
DD
is over-voltage.
8
GATE
Driver Output
The totem-pole output driver for the power MOSFET, which is internally clamped below 18V.
H:
J = with Frequency Hopping
Null = without Frequency
Hopping
T
: D = DIP, S = SOP
P:
Z = Lead Free
Null = regular package
XXXXXXXX:
Wafer Lot
Y
: Year;
WW
: Week
V
: Assembly Location
RI
VIN
GATE
VDD
SENSE
RT
GND
FB
SG5842
H
A
TP
XXXXXXXXYWWV