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參數(shù)資料
| 型號(hào)： | SG556 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Mobile PentiumR Processor Application Clock Generator |
| 中文描述： | 移動(dòng)PentiumR處理器時(shí)鐘發(fā)生器的應(yīng)用 |
| 文件頁(yè)數(shù)： | 2/10頁(yè) |
| 文件大?。?/td> | 62K |
| 代理商： | SG556 |
SG556
Mobile Pentium Processor Application Clock Generator
with SSCG, USB and Power Management Support
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07016 Rev. **
5/17/2001
Page 2 of 10
APPROVED PRODUCT
Pin Description
PIN No.
1
Pin Name
XIN
PWR
VDD
I/O
I
TYPE
OSC1
Description
On-chip reference oscillator input pin. Requires either an
external parallel resonant crystal (nominally 14.318 MHz) or
externally generated reference signal
On-chip reference oscillator output pin. Drives an external
parallel resonant crystal. When an externally generated
reference signal is used at Xin, this pin is left unconnected
Frequency select input pins. See frequency select table on
page 1.
Clock outputs. CPU frequency table specified on page 1.
2
XOUT
VDD
O
OSC1
15
SEL100/66#
-
I
PADI4
23, 24
CPUCLK
(0:1)
PCI_F
VDDC
O
BUF1
4
VDDP
O
BUF4
Free running PCI clock. When PCI_STP# = 0, this clock does
NOT stop.
48 MHz fixed clock.
PCI bus clocks. See frequency select table on page 1.
16
48M
PCI(1:5)
VDD48
VDDP
O
O
BUF3
BUF4
5, 7, 8,
10, 11
26
19
REF
VDDR
-
O
I
BUF3
PAD
PU
PAD
PU
PAD
PU
-
-
Buffered outputs of on-chip reference oscillator.
When driven to a logic low level, this pin will synchronously stop
all PCI clocks (except PCI_F) at a logic low level.
When driven to a logic low level, this pin will synchronously stop
all CPU clocks at a logic low level.
This pin is active low. When asserted low, the device is in
shutdown mode. VCO’s, Crystal, and outputs are turned off.
3.3 volt power supply for core logic.
Ground pins for the device.
PCI_STOP#
18
CPU_STOP#
-
I
17
PWR_DWN#
-
I
13, 21
3, 12,
14, 20,
22, 28
9, 6
VDD
VSS
-
-
P
P
VDDP
-
P
-
3.3 Volt power supply pins for PCI (1:5) and PCI_F clock output
buffers.
3.3 or 2.5 Volt power supply for CPUCLK (0:1) outputs.
3.3 Volt power supply pins for reference clock output buffers
and crystal circuit.
25
27
VDDC
VDDR
-
-
P
P
-
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