參數(shù)資料
型號(hào): SG1825CL
廠商: MICROSEMI CORP-ANALOG MIXED SIGNAL GROUP
元件分類: 穩(wěn)壓器
英文描述: HIGH - SPEED CURRENT - MODE PWM
中文描述: 2 A SWITCHING CONTROLLER, 1500 kHz SWITCHING FREQ-MAX, CQCC20
封裝: HERMETIC SEALED, CERAMIC, LCC-20
文件頁數(shù): 7/7頁
文件大?。?/td> 184K
代理商: SG1825CL
H
I G H
- S
P E E D
C
U R R E N T
-M
O D E
PWM
N
O T
R
E C O M M E N D E D
F O R
N
E W
D
E S I G N S
SG1825C/SG2825C/SG3825C
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
7
Copyright 1994
Rev. 1.3 6/96
APPLICATION INFORMATION
FIGURE 5.
OSCILLATOR FUNCTIONAL DIAGRAM
APPLICATION FIGURES
The oscillator frequency is programmed by external timing components R
T
and C
. A nominal +3.0 volts appears at the R
pin. The current flowing
through R
is mirrored internally with a 1:1 ratio. This causes an identical
current to flow out the C
pin, charging the timing capacitor and generating
a linear ramp. When the upper threshold of +2.8 volts is reached, a
discharge network reduces the ramp voltage to +1.0, where a new charge
cycle begins.
The Clock output pin is LOW (+2.3 volts) during the charge cycle, and
HIGH (+4.5 volts) during the discharge cycle. The Clock pin is driven by
an NPN emitter follower, and so can be wire-ORed. Each Clock pin can drive
a 1mA load. Since the internal current-source pulldown is approximately
400μA, the DC fan-out to other SG1825C Clock pins is at least two.
The type of capacitor selected for C
is very important. At high
frequencies, non-ideal characteristics such as effective series resistance
(ESR), effective series inductance (ESL), dielectric loss and dielectric
absorption all affect frequency accuracy and stability. RF capacitors such as
silver mica, glass, polystrene, or COG ceramics are recommended. Avoid
high-K ceramics, which work best in DC bypass applications.
OSCILLATOR
ERROR AMPLIFIER
The voltage error amplifier is a true operational amplifier with low-
impedance output, and can be gain-stabilized using conventional feedback
techniques. The typical DC open-loop gain is 95dB, with a single low-
frequency pole at 100Hz.
The input connections to the error amplifier are determined by the
polarity of the power supply output voltage. For positive supplies, the
common-mode voltage is +5.1 volts and the feedback connections in Figure
A are used. With negative outputs, the common-mode voltage is half the
reference, and the feedback divider is connected between the negative
output and the +5.1 volt reference as shown in Figure B.
FIGURE 6.
VOLTAGE AMPLIFIER CONNECTIONS
FIGURE 7.
DRIVING SHIELDED CABLE
OUTPUT DRIVER
The output drivers are designed to provide up to 1.5 Amps peak output
current. To minimize ringing on the output waveform, which can be
destructive to both the power MOSFET and the PWM chip, the series
inductance seen by the drivers should be as low as possible.
One solution is to keep the distance between the PWM and MOSFET gate
as short as possible, and to use carbon composition series damping resistors.
A Faraday shield to intercept radiated EMI from the power transistors is
usually required with its choice.
A second approach is to place the MOSFETs some distance from the PWM
chip, and use a series-terminated transmission line to preserve drive pulse
fidelity. This will minimize noise radiated back to the sensitive analog
circuitry of the SG1825C. A Faraday shield may also be required.
If the drivers are connected to an isolation transformer, or if kickback
through C
of the MOSFET is severe, clamp diodes may be required. 1 Amp
peak Schottky diodes will limit undershoot to less than -0.3 volts.
4
+ 5.1V
2.8V
1.0V
400μA
SG1825C
I
C
= I
R
C
T
R
T
CLOCK
+ 4.5V
+ 2.3V
I
R
3V
5
6
V
REF
2
1
3
R
3
R
Z
C
P
R
4
POSITIVE
OUTPUT
VOLTAGE
V
REF
2
1
3
R
3
R
Z
C
P
V
REF
2
V
ERROR
V
ERROR
FIGURE B
FIGURE A
R
1
R
2
R
1
R
2
NEGATIVE
OUTPUT
VOLTAGE
R
4
12
11
13
10
PWR GND
GND
*
50
W
50
W
V
C
24
W
FARADAY SHIELD
* SCHOTTKY CLAMP MAY BE REQUIRED
SG1825C
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