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參數(shù)資料
| 型號： | SED1345F0A |
| 元件分類： | 顯示控制器 |
| 英文描述： | 640 X 480 DOTS CRT TO LCD CONV DSPL CTLR, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 45K |
| 代理商： | SED1345F0A |
190
° X Driver
Parameter
Symbol
Condition
Min
Typ
Max
Unit
XSCL Cycle Time
tCSC
S6 = “H”
2t1
——
ns
S6 = “L”
4t1
XSCL “H” Pulse Width
tWSCH
S6 = “H”
t1–20
——
ns
S6 = “L”
2t1–20
XSCL “L” Pulse Width
tWSCL
S6 = “H”
t1–20
——
ns
S6 = “L”
2t1–20
UD0–3, LD0–3 Setup Time
tSUXD
S6 = “H”
t1–30
——
ns
before XSCL
S6 = “L”
2t1–30
UD0–3, LD0–3 Hold Time
tHXD
S6 = “H”
21–30
——
ns
after XSCL
S6 = “L”
2t1–30
XSCL to LP Time
tSL1
S6 = “H”
0.5t1–30
——
ns
S6 = “L”
t1–30
XSCL to LP Time
tSL2
S6 = “H”
t1–20
——
ns
S5 = “H”
S6 = “L”
2t1–20
LP to XSCL Time
tLS1
S6 = “H”
1.5t1–50
——
ns
S6 = “L”
3t1–50
LP to XSCL Time
tLS2
S6 = “H”
t1–20
——
ns
S6 = “L”
2t1–20
XSCL to LP Time
tSL3
S6 = “H”
0.5t1–40
——
ns
S5 = “L”
S6 = “L”
t1–40
LP to XSCL Time
tLS3
S6 = “H”
0.5t1–40
——
ns
S6 = “L”
t1–40
LP Cycle Time
tCLP
S0 = “H”
320t1
——
ns
S0 = “L”
640t1
S5 = “H”
S6 = “H”
1.5t1–50
—
ns
LP, YSCL “H” Pulse Width
tWLPH
S6 = “L”
3t1–50
S5 = “L”
S6 = “H”
t1–40
——
ns
S6 = “L”
2t1–40
LP Setup Time before XECL
tSULP
S5 = “H”, S6 = “H”
t1–50
—
ns
LP Hold Time after XECL
tHLP
S5 = “H”, S6 = “H”
0.5t1–40
—
ns
XSCL to XECL Time
tES1
S5 = “H”, S6 = “H”
0.5t1–30
—
ns
XECL to XSCL Time
tES2
S5 = “H”, S6 = “H”
0.5t1–40
—
ns
XECL “H” Pulse Width
tWECH
S5 = “H”, S6 = “H”
1.5t1–50
—
ns
WF Output Delay Time After LP, YSCL
tDFR
S5 = “H”, S6 = “H”
—
100
ns
(VDD = 5V
±5%, VSS = 0V, Ta = 0 to 70°C)
t1 = 2tCCK (tCCK = dot clock cycle)
SED1345
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