參數(shù)資料
型號(hào): SED1336F0A
元件分類(lèi): 顯示控制器
英文描述: 640 X 256 DOTS DOT MAT LCD DSPL CTLR, PQFP60
封裝: PLASTIC, QFP6-60
文件頁(yè)數(shù): 2/12頁(yè)
文件大?。?/td> 50K
代理商: SED1336F0A
162
° SLEEP IN Command Timing
Signal
Symbol
Parameter
VDD = 4.5 to 5.5V
VDD = 3.0 to 4.5V
Unit
Condition
min
max
min
max
tWRD
VCE falling-edge delay
*1
*1
ns
WR
time
tWRL
YDIS falling-edge delay
—*2—*2
ns
time
Ta = –20 to 75
°C
CL =
100 pF
SED1336
VCE
WR
(command input)
YDIS
tWRL
tWRD
SYSTEM SET write
SLEEP IN write
1. tWRD = 18tC + tOSS + 40 (tOSS is the time delay from the sleep state until stable operation)
2. tWRL = 36tC
× [TC/R] × [L/F] + 70
° External Oscillator Signal Timing
Signal
Symbol
Parameter
VDD = 4.5 to 5.5V
VDD = 3.0 to 4.5V
Unit
Condition
min
max
min
max
tRCL
External clock rise time
15
15
ns
tFCL
External clock fall time
15
15
ns
tWH
External clock
*1
*2
*1
*2
ns
HIGH-level pulsewidth
tWL
External clock
*1
*2
*1
*2
ns
LOW-level pulsewidth
tC
External clock period
100
125
ns
Ta = –20 to 75
°C
EXT
φ0
1.
(tC – tRCL – tFCL)
×
475
< tWH, tWL
1000
2.
(tC – tRCL – tFCL)
×
525
> tWH, tWL
1000
EXT
φ0
tWL
tWH
tCL
tRCL
tFCL
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