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參數(shù)資料
| 型號： | SDC-19206-302 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP40 |
| 封裝： | 1.140 X 2.020 INCH, 0.230 INCH HEIGHT, TDIP-40 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 124K |
| 代理商： | SDC-19206-302 |
8
converter loop cannot maintain input-output sync, or if the con-
verter malfunctions where it cannot maintain the loop at a null.
LOSS OF SIGNAL (LOS, PIN 28)
The Loss of Signal (LOS) output is used for system safety. The
LOS output changes from logic 0 to 1 if all three synchro inputs
are disconnected. With disconnected synchro inputs, unpre-
dictable converter performance occurs.
PROGRAMMABLE BANDWIDTH (BW, PIN 5)
Either low or high bandwidth can be selected by using the BW
logic input. A logic 0 applied to BW selects low bandwidth (13 Hz
nominal), while a logic 1 selects high bandwidth (53 Hz nominal).
Bandwidth can be changed during converter operation.
Bandwidth and the acceleration constant (Ka) can be determined
from the following formulas:
See Dynamic Characteristics TABLE 4 and FIGURES 15 to
17 for values.
CONTROL TRANSFORMER MODE (S, PIN 6)
The converter will function as a Control Transformer (CT) by
placing S (pin 6) to logic 0. In the CT mode, the digital inputs are
double buffered, EM is redefined as LM, EL is redefined as LL
and INH becomes LA (see FIGURE 12). FIGURE 13 shows CT
mode timing for a two-byte transfer.
The CT mode is used when the AC error (e) is needed to drive
an external control loop by the difference angle of the resolver
input and the digital input. It is also used for presetting the con-
verter to a specific angle to reduce the step response time.
HIGH
ACCURACY
CONTROL
TRANSFORMER
DEMODULATOR
POWER SUPPLY
CONDITIONER
SIN
(
θ-φ)
BIT
DETECT
LOSS OF
SIGNAL
DETECTOR
16 BIT CT
TRANSPARENT
LATCH
29 BIT
40 REF
39 e
9
LA(INH)
8
7
AB
1-3
SYNCHRO
INPUT
12-19
1-8
34 +15 V
RESOLUTION
CONTROL
DIFF
GAIN
OF 2
16 BIT
U-D COUNTER
(SET MODE)
SIGNAL
INPUT
GAIN
REFERENCE
CONDITIONER
28
LOS
SIN
θ
COS
θ
DIGITAL
ANGLE
φ
e
+15 V
-15 V
20-27
9-16
11 LL(EL)
10
LM(EM)
+11 V
+5.5 V
D
FIGURE 12. CONTROL TRANSFORMER BLOCK DIAGRAM
Closed Loop Bandwidth (Hz) = 2 A /
π
Ka = A2
TABLE 4. DYNAMIC CHARACTERISTICS
PARAMETER UNITS
BANDWIDTH
HIGH
LOW
RESOLUTION
BITS
10
12
14
16
10
12
14
16
Input Frequency
Tracking Rate
Bandwidth, CL
Ka
A1**
A2**
A**
B**
acc-1 LSB lag
Settling time
max
kHz
RPS
Hz
1/sec2
1/sec
°/sec2
msec
.36-1
160
53
14.4k
0.4
36k
120
60
17k
110
*
40
*
4.2k
110
*
10
*
1.1k
200
*
2.5
*
260
500
.047-1
40
13
3.6k
0.1
9k
30
15
1.1k
550
*
10
*
260
600
*
2.5
*
66
1100
*
0.62
*
17
2400
RPS minimum
*Same as value to left
**See FIGURE 15 for definitions of A1, A2, A, and B.
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