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參數(shù)資料
| 型號： | SDC-14608-454Q |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DMA28 |
| 封裝： | DDIP-28 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 237K |
| 代理商： | SDC-14608-454Q |
2
TABLE 1. SDC-14600/05 SPECIFICATIONS (Each Channel)
These specs apply over the rated power supply temperature and ref-
erence frequency ranges; 10% signal amplitude variation and 10%
harmonic distortion. Each Channel unless stated otherwise
PARAMETER
UNIT
VALUE
RESOLUTION
Bits
14
16
ACCURACY
Min
4(8) + 1 LSB
2(4) + 1 LSB
REPEATABILITY
LSB
1 max
DIFFERENTIAL LINEARITY
LSB
1 max
REFERENCE INPUT
Type
Voltage Range
Frequency
Input Impedance
single ended
differential
Common Mode Range
Vrms
Hz
Ohm
Vpeak
(+REF -REF )
Common to Both Channels
differential
2 & 11.8V units
2 - 35
360 - 5000
60k
120k
50,
100 transient
90V unit
10-130
See Note.
270k min
540k min
200,
300 transient
SIGNAL INPUT CHARACTERISTICS
90V Synchro Input (L-L)
Zin line-to-line
Zin line-to-ground
Common Mode Voltage
11.8V Synchro Input (L-L)
Zin line-to-line
Zin line-to-ground
Common Mode Voltage
11.8V Resolver Input (L-L)
Zin single ended
Zin differential
Common Mode Voltage
2V Direct Input (L-L)
Voltage Range
Max Voltage No Damage
Input Impedance
Ohm
V
Ohm
V
Ohm
V
Vrms
V
Ohm
Each Channel
123k
80k
180 max
52k
34k
30 max
70k
140k
30 max
2 nom 2.3 max
25 cont 100 pk transient
20 M // 10 pF min
DIGITAL INPUT/OUTPUT
Logic Type
Inputs
Inhibit (INH)(common)
Enable Bits 1 to 8 (EM)
Enable Bits 9 to 14(16)(EL)
Output
Parallel Data [1-14(16)]
bits
TABLE 1. SDC-14600/05 SPECIFICATIONS (continued)
PARAMETER
UNIT
VALUE
DIGITAL INPUT/OUTPUT
Outputs (continued)
Drive Capability
TTL
CMOS
DYNAMIC CHARACTERISTICS
Each Channel
Input Frequency
Bandwidth (Closed Loop)
Ka
A1
A2
A
B
Resolution
Tracking Rate
typical
minimum
Acceleration (1 LSB lag)
Settling Time (179° step max)
Hz
1/s2
1/s
bits
rps
deg/s2
msec
14
1.25
1
18
1100
Device Type
16
0.31
0.25
4.5
2500
14
10
8
1160
140
16
2.5
2
290
320
VELOCITY
CHARACTERISTICS
Polarity
Voltage Range (Full Scale)
Scale Factor
Scale Factor TC
Reversal Error
Linearity
Zero Offset
Zero Offset TC
Load
Noise
±V
±%
ppm/°C
±%
mV
V/°C
kOhm
(Vp/V)%
POWER SUPPLIES
Nominal Voltage
Voltage Range
Max Volt. w/o Damage
Current
V
±%
V
mA
Total Device
+5
-5
5
10
+7
-7
24 typ, 34 max
TEMPERATURE RANGE
Operating
-30X
-10X
Storage
°C
0 to +70
-55 to +125
-65 to +150
PHYSICAL
CHARACTERISTICS
Size
Weight
in
(mm)
oz
1.48 x 0.78 x 0.2
(37.6 x 19.8 x 5.1)
0.66
Note: 47-5k for 90 V, 60 Hz; 360-5k for 90 V, 400 Hz
Each Channel
Positive for increasing angle
4.5 typ, 4 min
10 typ
20 max
100 typ
200 max
1 typ
2 max
0.5 typ
1 max
5 typ
10max
15 typ
30 max
20 max
1 typ
2 max
Each Channel
50 pF +
Logic 0; 1 TTL load
1.6 mA at 0.4 V max
Logic 1; 10 TTL loads
-0.4 mA at 2.8 V min
Logic 0; 100 mV max
driving
Logic 1; +5 V supply
minus 100 mV min
driving
60 Hz
47 - 5k
15
830
0.17
5k
29
14.5
400 Hz
360-5k
103
53k
1.33
40k
230
115
TTL/CMOS compatible
Logic 0 = 0.8 V max.
Logic 1 = 2.0 V min.
Loading =10 A max P.U.
current source to +5 V // 5 pF
maximum
CMOS transient protected
Each Channel
Logic 0 inhibits ; Data
stable within 0.5 s
Logic 0 enables; Data stable
within 150 ns
Logic 1 = High Impedance
Data High Z within 100 ns
Common to Both Channels
8 parallel lines; 2 bytes natural
binary angle, positive logic
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