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參數(shù)資料
| 型號： | SDC-14587-552Q |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
| 封裝： | DDIP-36 |
| 文件頁數(shù)： | 17/18頁 |
| 文件大小： | 202K |
| 代理商： | SDC-14587-552Q |
8
Data Device Corporation
www.ddc-web.com
SDC-14580
H-05/04-0
converted to resolver format; sin
θcosωt and cosθcosωt. Direct
Resolver inputs accept 2.0 Vrms inputs in resolver form, (sin
θ
cos
ωt and cosθcosωt) and are buffered prior to conversion. FIG-
URE 3 illustrates synchro and resolver signals as a function of
the angle
θ.
The solid-state signal and reference inputs are true differential
inputs with high AC and DC common mode rejection.
Input
impedance is maintained with power off. The Synchro and
Resolver input options are shown in FIGURES 4 and 5. The
direct resolver inputs are transient protected voltage followers
which accept 2.0 Vrms resolver inputs as shown in FIGURE 6.
RESISTOR PROGRAMMING FOR NON-STANDARD
INPUT VOLTAGES
When applying voltages greater than 2.0 Vrms to the direct input
option, a simple voltage divider can be used to attenuate both the
sin and cos inputs. Since the converter inputs are voltage followers
there will be no loading on the resistor dividers. (See FIGURE 7.)
The resolver input conditioner consists of two differential ampli-
fiers. The input is currently scaled down with 23 kOhm resistors
for the 11.8 V resolver. When applying resolver input voltages
greater than the rated voltages, four additional resistors are used
to scale down the voltage. These resistors are placed one in
series with each input line (see FIGURE 8).
INTERFACING - DIGITAL OUTPUTS AND CONTROLS
DIGITAL INTERFACE
The digital interface circuitry performs three main functions:
1. Latches the output bits during an Inhibit (lNH) command
allowing stable data to be read out of the SDC-14580.
2. Furnishes parallel tri-state data formats.
3. Acts as a buffer between the internal CMOS logic and the
external TTL logic.
In the SDC-14580 applying an Inhibit (INH) command will lock
the data in the inhibit transparent latch without interfering with
the continuous tracking of the converter’s feedback loop.
Therefore the digital angle
φ is always updated, and the INH can
be applied for an arbitrary amount of time. The Inhibit
Transparent Latch and the 50 ns delay are part of the inhibit cir-
cuitry. For further information see the INHIBIT (INH, PIN 33)
paragraph.
DIGITAL ANGLE OUTPUTS (LOGIC INPUT/OUTPUT)
The digital angle outputs are buffered and provided in a two-byte
format. The first byte contains the MSBs (bits 1-8) and is enabled
by placing EM (pin 26) to a logic 0. Depending on the user-pro-
grammed resolution, the second byte contains the LSBs and is
enabled by placing EL (pin 25) to a logic 0.
1
R1
S3
SDC-14580
S3
2
R2
S1
3
R3
S2
4
R4
S4
FIGURE 8. RESOLVER INPUT CONNECTION
DIAGRAM
2
R3
3
R1
S3
SDC-14580
R4
1
R2
S1
S2
S4
COS
SIN
V
FIGURE 7. DIRECT INPUT RESISTOR SCALING
Input Voltage L-L
R1+R3
=
1V
R3
Notes:
(1) R1 = R2; R3 = R4 to 0.1% match.
(2) R1 + R3 and R2 + R4 should be as high as possible to
minimize resolver loading.
R + 23k
Input Voltage L-L
=
23k
11.8 V
Notes:
(1) Input Voltage L-L is greater than 11.8 V.
(2) R = R1 = R2 = R3 = R4 to 0.1% match.
FIGURE 9. TRI-STATE OUTPUT TIMING
;
;;
100 ns MAX
EM or EL
150 ns MAX
DATA
VALID
HIGH Z
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