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參數(shù)資料
| 型號： | SDC-14585-804Q |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
| 封裝： | DDIP-36 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大小： | 202K |
| 代理商： | SDC-14585-804Q |
5
Data Device Corporation
www.ddc-web.com
SDC-14580
H-05/04-0
THEORY OF OPERATION
The SDC-14580 Series are small, 36 pin DDIP Synchro-to-Digital
or Resolver-to-Digital hybrid converters. As shown in the block
diagram (FIGURE 1), the SDC-14580 can be broken down into the
following functional parts: Signal Input Option, Converter, Analog
Conditioner, Power Supply Conditioner, and Digital Interface.
CONVERTER OPERATION
As shown in FIGURE 1, the converter section of the SDC-14580
contains a high accuracy control transformer, demodulator, error
processor, voltage controlled oscillator (VCO), up-down counter,
and reference conditioner. The converter produces a digital
angle which tracks the analog input angle to within the specified
accuracy of the converter.
The control transformer performs the following trigonometric
computation:
sin(
θ - φ) = sinθ cosφ - cosθ sinφ
Where:
θ is angle theta representing the resolver shaft position.
φ is digital angle phi contained in the up/down counter.
The tracking process consists of continually adjusting
φ to make
(
θ - φ) = 0, so that φ will represent the shaft position θ.
The output of the demodulator is an analog DC level proportion-
al to sin(
θ-φ). The error processor receives its input from the
demodulator and integrates this sin(
θ - φ) error signal which then
drives the VCO. The VCO’s clock pulses are accumulated by the
up/down counter. The velocity voltage accuracy, linearity and off-
set are determined by the quality of the VCO. Functionally, the
up/down counter is an incremental integrator. Therefore, there
are two stages of integration which makes the converter a Type
II tracking servo.
In a Type II servo, the VCO always settles to a counting rate
which makes d
φ/dt equal to dθ/dt without lag. The output data will
always be fresh and available as long as the maximum tracking
rate of the converter is not exceeded.
The reference conditioner is a comparator that produces the
square wave reference voltage which drives the demodulator. Its
single ended Input Z is 50k Ohms min, 100k Ohms differential.
SPECIAL FUNCTIONS
REFERENCE SYNTHESIZER-QUADRATURE VOLTAGES
The synthesized reference section of the SDC-14580 eliminates
errors caused by quadrature voltage. Due to the inductive nature
of synchros and resolvers, their signals typically lead the refer-
ence signal (RH and RL) by about 6°. When an uncompensated
reference signal is used to demodulate the control transformer’s
output, quadrature voltages are not completely eliminated. In a
12- or 14-bit converter it is not necessary to compensate for the
reference signal’s phase shift. A 6° phase shift will, however,
cause problems for the one minute accuracy converters. As
shown in FIGURE 1, the converter synthesizes its own
cos(
ωt+α) reference signal from the sinθ-cos(ωt+α), cosθ-cos(ωt
+
α) signal inputs and from the cosωt reference input. The phase
angle of the synthesized reference is determined by the signal
input. The reference input is used to choose between the +180°
and -180° phases. The synthesized reference will always be
exactly in phase with the signal input, and quadrature errors will
therefore be eliminated. The synthesized reference circuit
also eliminates the 180° false error null hangup.
Quadrature voltages in a resolver or synchro are by definition the
resulting 90° fundamental signal in the nulled out error voltage
(e) in the converter. A digital position error will result due to the
interaction of this quadrature voltage and a reference phase shift
between the converter signal and reference inputs. The magni-
tude of this error is given by the following formula:
Magnitude of Error=(Quadrature Voltage/F.S.signal) tan(
α)
Where:
Magnitude of Error is in radians.
Quadrature Voltage is in volts.
Full Scale signal is in volts.
α = signal to REF phase shift
An example of the magnitude of error is as follows:
Let: Quadrature Voltage = 11.8 mV
Let: F.S. signal = 11.8 V
Let:
α = 6°
Then: Magnitude of Error = 0.35 min
1 LSB in the 16th bit.
Note:
Quadrature is composed of static quadrature which is
specified by the synchro or resolver supplier plus the speed
voltage which is determined by the following formula:
Speed Voltage=(rotational speed/carrier frequency) F.S. signal
Where: Speed Voltage is the quadrature due to rotation.
Rotational speed is the RPS (rotations per second) of
the synchro or resolver.
Carrier frequency is the REF in Hz
BUILT-IN-TEST (BIT, PIN 34)
The Built-In-Test output (BIT) monitors the level of error (D) from
the demodulator. D represents the difference in the input and
output angles and ideally should be zero. If it exceeds approxi-
mately 65 LSBs (of the selected resolution), the logic level at BIT
will change from a logic 1 to logic 0. This condition will occur dur-
ing a large step and reset after the converter settles out. BIT will
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